Virtual prototyping for FPGAs

As we all know, today's high-end FPGAs are getting terrifyingly large. Not surprisingly, multi-million gate FPGA designs are hitting the same problems that befell ASICs, such as the fact that it takes forever to do place-and-route (P&R). Furthermore, although the original (logical) RTL representation of the design is almost invariably hierarchical, the P&R tools typically work on flattened representations internally. This means that if you make the smallest change to one block of RTL code and re-synthesize only that block, you end up having to re-run P&R on the entire design, which means that you can be old and gray before you finally get to achieve timing closure. And just to increase the fun and frivolity, due to the way in which their algorithms work, FPGA P&R tools are non-deterministic, which means that every time you run them you get slightly different results, even if you don't make any changes to the design itself (I hate that).

And so, with a fan-fare of trumpets, HierDesign's FPGA-centric equivalent of an ASIC silicon virtual prototyping (SVP) tool — PlanAhead — leaps onto the center stage with gusto and abandon. Initially I was a bit puzzled as to how the SVP moniker related to PlanAhead, which is essentially a hierarchical floorplanning application. However, on talking to the folks at HierDesign, they pointed out that the definition of an SVP is something that gives you the ability to analyze problems like timing, resource usage, and routing congestion early in the design cycle prior to running a full-blown physical implementation (place-and-route). As we'll see, PlanAhead performs this role magnificently, so it's an SVP environment as far as I'm concerned.

Slipping into the flow

A much-simplified view of a traditional FPGA design flow is that you create a hierarchical representation of your design at the RTL level of abstraction and run it through logic synthesis (or physically-aware synthesis) in order to generate a structural LUT-level netlist and associated timing constraints. You then throw this new version of the design "over-the-wall" to the FPGA companies P&R tools, cross your fingers, and wait (and wait, and wait) to see what happens.

Well, PlanAhead slips right into this flow with the absolute minimum of pain and suffering, not the least that HierDesign started by first designing their graphical user interface (GUI) to be so intuitive and easy to use that when novice users play with the tool they consistently achieve expert-level results.

We start off with a graphical top-down view of the target FPGA device showing the I/O along with all of the internal logical resources, such as lookup tables (LUTs), registers, slices, configurable logic blocks (CLBs), embedded block RAMs, multipliers, and so forth. As soon as you input your structural (hierarchical) LUT-level netlist — along with any timing and physical constraints — PlanAhead automatically creates an initial floorplan for you. This auto-generated floorplan shows a collection of square and/or rectangular blocks, each of which corresponds to a top-level block in the design. Furthermore, if any of these top-level blocks itself contains sub-blocks, then these are shown as embedded blocks in the floorplan (and so on down through the hierarchy) as shown below.

Figure 1 -- Screenshot of PlanAhead GUI

In addition to the graphical top-down view of the device (shown here on the right-hand-side), you are also provided with logical and physical representations of the hierarchy. And there are a number of additional views that aren't shown here, including a graphical view of the package's pins, a schematic view, and so forth.

As was previously noted, the cool thing about the top-down view of the floorplan superimposed over the device is that is shows all of the resources (LUTs, registers, RAMs, multipliers, etc.) used by each block. Also indicated is the amount of routing resources required to link the various blocks together.

Whenever you are ready to rock-and-roll, you can select one or more floorplan blocks and kick-off the FPGA P&R software. Each block is treated as an individual entity, so once you've laid out a block it will remain untouched unless you decide you want to change it.

This has a number of advantages. First of all the P&R run times for individual blocks are extremely small compared to the traditional times associated with a full-up multi-million gate designs (say 15 minutes per block as opposed to an overnight run for the whole design). Even if you add up the P&R times for running all of the blocks individually, the total comes in way under performing P&R on the whole design in its entirety. This is because the complexity (and associated run-times) of the P&R increases in a non-linear manner as the size of the block being processed increases. Furthermore, once you've run P&R on all of the blocks, you can make changes to individual blocks and re-run P&R on those blocks without affecting the rest of the chip.

Another advantage of this PlanAhead approach is that it lends itself to creating and preserving intellectual property (IP). Once a block has undergone P&R, you can lock it down and export it as a new structural LUT-level netlist along with its associated physical and timing constraints. This block can subsequently be used in other designs (its placement is relative, which means that it can be dragged around the chip and relocated as discussed below)

Rather clever

This is where things start to get rather clever, because PlanAhead's initial placement of the design allows it to provide you with accurate timing estimations on a block-by-block basis prior to running P&R. Thus, if you see any potential problem areas, you can quickly and easily modify the floorplan in order to address them. When it comes to performing this interactive floorplan modification, you have a number of options available to you. First of all you can re-shape blocks in the floor plan. In the initial PlanAhead release you could only change the aspect radio of the various squares and rectangles, but the latest release allows you to create more complex blocks such as 'L', 'U', and 'T' shapes — basically any shape you can form out of squares and rectangles (note the selected 'L' shape highlighted in yellow in Figure 1).

Next you can move the blocks around. When you grab a block and start to drag it across the face of the device, the system will provide a graphical indication as to whether or not there are the necessary resources required to implement that block at its current location (you can only drop the block in an area where there are sufficient resources). Furthermore, as you manipulate and reshape a block, PlanAhead dynamically displays the utilization of resources (LUTs, registers, RAMs, Multipliers, etc.) inside that block relative to the total amount of each resource type currently encompassed by that block.

Pretty darn clever

Now this is where things start to get pretty darn clever, because you can also split existing blocks into two or more sub-blocks, which you can then manipulate independently. Alternatively, you can merge two or more blocks into a single block. Or in some cases (say areas of control logic) you might wish to pull one or more sub-blocks out of their parent blocks and move them up to the top level of the design, at which point you can reshape them, merge them together, move them around, and so forth.

Of course much of this reflects a different philosophy to the way in which one might use an ASIC floorplanning tool. In the case of an ASIC, for example, if you have two blocks with lots of interconnect between them you would typically place them side by side. By comparison, in the case of an FPGA, merging the blocks (thereby allowing the P&R tools do a much better job of optimization using local versus global routing resources) might provide a more efficacious solution.

What, you want more? Well in fact you aren't limited to manipulating blocks only as described in the original RTL hierarchy. You can actually manipulate individual FPGA resources like LUTs, registers, slices, and CLBs. This includes dragging them around and repositioning them within their current hierarchical block, dragging them from one hierarchical block to another, creating new blocks and dragging groups of LUTs from one or more existing blocks into this new block, and so forth.

Mind-bogglingly clever

Call me an old cynic if you will, but at some stage I started to think to myself, "Hmmmm, but what happens if I wish to go back and make changes to my source RTL after I've modified the hierarchy in PlanAhead?" The last thing I need is to use PlanaHead to arrive at a corker of a solution, then find that making a small "tweak" to one of my RTL blocks obliges me to repeat the entire floorplanning process (I've run into this type of problem too many times with other tools to want to go through it again).

But NO! This is where PlanAhead starts to get mind-bogglingly clever, because you can make changes to your original RTL and re-synthesize those blocks. Then, when you re-import the resulting LUT-level netlist(s), PlanAhead sorts everything out for you and loads the right logic into the appropriate floorplan blocks (how do they do it? I don't have a clue!).

As always there are pros and cons to everything. PlanAhead doesn't really have any competition in its "space," which is as an add-on to whatever synthesis solution you happen to be using. On the downside, PlanAhead only works with Xilinx parts, but this isn't much of a problem if you only happen to be using these parts anyway. Of course the various FPGA vendors have a smattering of internally-developed floorplanning tools, but most of the folks I talked to were less than impressed with these offerings.

As far as I can see, the only sort-of-equivalent to PlanAhead is Amplify from Synplicity. On the upside this works with both Xilinx and Altera devices, and it works pre-synthesis, which probably offers some advantages. On the downside, Amplify is significantly more expensive than PlanAhead, and if you want to use Amplify then you're obliged to use Synplicity's Synplify FPGA synthesis offering. Another big difference is the fact that PlanAhead auto-generates the initial floorplan, which gives you a real good starting point, while Amplify requires you to do the grunt work yourself.

For my part, I like PlanAhead's concept of working just above the nitty-gritty P&R level, including the ability to quickly and easily change the layout hierarchy and to kick-off the P&R on a block-by-block basis. I also like PlanAhead's philosophy of getting really good P&R "answers" for the various blocks as fast as possible and then keep these answers as long as possible (other approaches typically a long time to get a "best answer," but as soon as you make a small change they immediately throw that answer away and start all over again).

Of course, I'd really like to hear from anyone who has actually worked with both Amplify and PlanAhead (and anything else that's out there roaming the streets) and is in a position to give some real-world feedback on the relative merits of their various approaches. But while I'm waiting, PlanAhead receives an official "Cool Beans" from yours truly. Until next time, have a good one!

Clive (Max) Maxfield is president of Techbites Interactive, a marketing consultancy firm specializing in high-tech. Author of Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and co-author of EDA: Where Electronics Begins, Max was once referred to as a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.