The need for floorplanning

Today's increasingly large and complex digital integrated circuit (IC) and system-on-chip (SoC) designs often contain tens of millions of logic gates. Ensuring that these designs will function as required demands the use of chip-level floorplanning.

In reality, all high-end chip designs employ some form of floorplanning activity early in the design flow. This commences with the design being partitioned into functional blocks, each of which are assigned very approximate gate-count and area values based on experience with previous designs. These area values are then used to create a rudimentary initial floorplan. Once the initial floorplan has been determined, preliminary timing budgets and constraints are assigned to the functional blocks, each of which is handed over to one or more RTL design engineers.

In the case of conventional flows, only very crude timing and area estimates are available at the RTL level. It is only after the physically-aware synthesis and in-place optimization (IPO) steps have been performed — and placed gate-level netlists are available for each functional block — that meaningful area and timing estimates are available. In turn, it is only when meaningful area and timing estimates are available that meaningful floorplanning activities can take place.

The end result is very expensive and time-consuming iterations. Obviously, the most cost-effective approach — in terms of engineering resources and time-to-market — is to start performing accurate floorplanning as early as possible in the design cycle. The trick, of course, is in how one achieves this accuracy.

Problems with conventional flows

I was going to draw a diagram of this, but lunch is calling, so I'm going to describe things in words and you'll just have to imagine a really cool illustration. There are three main stages in a conventional flow (don your 3D glasses and pretend to look at imaginary Figure 1 now).

Stage 1: First of all we have the system architects who partition the design into functional blocks, associate estimated gate-counts and areas with these blocks, and establish an initial floorplan with associated chip-level and block-level timing constraints.

Stage 2: Next we have a group of bright-eyed and bushy-tailed RTL design engineers, each of whom deals with their own block. For the purposes of this discussion, we'll assume that each RTL block will eventually equate to around 400K gates.

Once a block of RTL has been created, InTime contends that synthesis and IPO will take about 7 hours followed by 3 hours to perform timing analysis and generate a timing report (about 10 hours total). Of course the RTL engineers will have to loop around over and over again making architectural changes to achieve their block-level timing constraints, where each loop takes 10 hours or so on top of making the code modifications themselves.

Stage 3: Finally, we have the system integrators who take all of the blocks from the RTL engineers — along with their more accurate gate-count, area, and timing values — use these to generate a more accurate floorplan, and then use this to perform chip-level synthesis/IPO and timing analysis. If we assume a chip with 4.5M gates, then InTime says that synthesis/IPO can take 72 hours, followed by 27 hours to perform detailed timing analysis and generating an associated timing report (about 99 hours total).

This is the point that the system integrators may become aware of any insurmountable problem areas, which often results in blocks being "sent back" to the RTL design engineers with requests for architectural modifications based on the new timing budgets and constraints derived from the more accurate floorplan.

PHEW! Assuming these numbers to be accurate, it's a wonder that we manage to develop high-end chips at all! It now becomes obvious that the real problem with conventional design flows is that they use the wrong tools for the job. That is, existing flows force RTL design engineers to use expensive, compute-intensive, time-consuming implementation tools — like physically aware synthesis — to support their architectural exploration, planning, and timing analysis activities. But using implementation tools to perform these activities makes the cycle times through conventional flows too long and problematic.

RTL floorplanning leaps to the rescue

And so we come to InTime's RTL floorplanning solution. In its simplest form, RTL floorplanning refers to the ability to take RTL that is ready for synthesis following functional signoff, and to use this RTL to provide gate-count, area, and timing estimations that are sufficiently accurate to perform meaningful floorplanning analysis.

In order to satisfy the requirements for RTL floorplanning, InTime has two related applications called Time Planner and Time Director. Time Planner is used by system architects and system integrators to perform chip-level floorplanning and analysis functions. Time Director is used by RTL design engineers to provide gate-count, area, and timing estimations at the block level.

Based on InTime's technology, a new RTL-based floorplanning flow is as follows (don your 3D glasses and pretend to look at imaginary Figure 2 now).

Stage 1: The flow starts as the system architect uses Time Planner to establish the initial floorplan and to generate the associated chip and block-level timing budgets and constraints. At this stage of the process, Time Planner will accept gate-count, area, and timing estimates for blocks for which RTL is not yet available, and it will generate gate-count, area, and timing predictions for blocks whose RTL is available (these may include internal or third-party intellectual property (IP) blocks). Time Planner also accepts "black box" values for any hard IP blocks representing microprocessor cores, memories, peripherals, and so forth, along with the locations of the chip's input/output (I/O) pins.

Using this preliminary information, the system architects work interactively with Time Planner to generate the initial floorplan. The architects then use Time Planner to generate the first-pass block-level timing budgets and constraints based on this initial floorplan.

Stage 2: As for a conventional flow, the RTL design engineers create and functionally verify the RTL corresponding to their blocks. In the conventional flow, however, the engineers would now have to run compute-intensive and time-consuming implementation tools that take about 10 hours per iteration in order to obtain accurate timing information.

By comparison, in the case of the RTL floorplanning flow, the engineers use Time Director to perform RTA. Time Director quickly analyzes the RTL and generates gate-count and area estimations, which it subsequently uses to generate timing estimations. The key point is that Time Director can generate an accurate timing report on a 400K-gate block in only 15 minutes.

This means that the RTL design engineers can quickly iterate their designs and experiment with alternative architectures so as to meet their block-level timing constraints. Furthermore, this flow means that RTL design engineers aren't obliged to run implementation tools like physically-aware synthesis; this offers dramatic savings on licenses in addition to reducing design times.

Stage 3: As each RTL block is completed, it is handed over to the system integrator, who starts to create more accurate floorplan representations of the chip-level design. By means of Time Planner, the system integrator can control the shapes of the various blocks, ranging from simply modifying the aspect ratios of rectangular blocks to creating more complex contours such as 'L', 'T', and 'U'-shaped blocks.

Of particular interest — especially in the case of designs required to use the abutted floorplanning technique — is that the system integrator can use Time Planner to interactively assign pin locations to blocks (these are not primary I/O pins to the device, but rather the block-level I/O used for inter-block communications). With regards to these pins, Time Planner provides the system integrator with a range of abilities, such as fixing their locations or allowing them to migrate along their side of the block or around the entire block with varying degrees of freedom.

Working with RTL offers exceptional advantages at the chip level, because Time Planner can generate an accurate timing report for an entire 4.5M-gate design in only around 2.5 hours (as opposed to perhaps 99 hours using a conventional flow). This means that system integrators can quickly iterate their floorplans and experiment with alternative block shapes and placements so as to meet (or exceed) their chip-level timing constraints.

How does RTL floorplanning work?

In a very cunning manner! In fact it's based on the same concepts and techniques that I presented in my original RTA article (see the link at the beginning of this column), so I won't bother going over this techno-geek stuff again here.

The point is that the combination of RTL floorplanning and RTA results in the ability to provide a better "seed" to the logic synthesis or physically-aware synthesis applications, which are now used more appropriately downstream in the flow. Providing a good floorplan can cut a physically-aware synthesis engine's chip-level runtimes in half as compared to conventional design flows. Furthermore, such a floorplan can shave as much as 10% off the slowest timing path!

The end result is that — by performing meaningful floorplanning at the RTL level 40x to 50x faster than conventional gate-level approaches — RTL Floorplanning significantly decreases the loading on engineering resources, dramatically reduces the chip's design cycle time, and can result in higher-performance chips. I venture to say that if my mother were in charge of designing a high-end chip, she would be "champing-at-the-bit" to sink her teeth into InTime's RTL Flooplanning technology. And if it would be good enough for my mother, then it's certainly good enough for yours truly, so RTL floorplanning receives an official "Cool Beans" from me. Until next time, have a good one!

Clive (Max) Maxfield is president of Techbites Interactive, a marketing consultancy firm specializing in high-tech. Author of Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and co-author of EDA: Where Electronics Begins, Max was once referred to as a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.