In today's world of fast electronics products, not all aspects of the technology maintain a concurrent pace. This is especially true for component data sheets. The sheets written for current-generation CMOS circuits rely on outmoded TTL performance characteristics that don't reflect the performance of these circuits in high-speed apps.

Most IC data sheets reflect TTL characteristics-outputs rated in milliamps, tested with capacitive loads and lead frames specified as lumped inductors and capacitors. With TTL, inputs drew significant current in the "low" state that had to be supplied by the driver. The current drawn by an input divided the driver output current, and the resulting fanout could be calculated. This calculation was accurate for the steady-state condition.

The problem is CMOS circuits don't have any standby current drain, so current rating is of no use. Worse, with modern logic, the edges switch so fast that the loads and wires can't be treated as lumped structures. Instead, wires must be treated as transmission lines that have some impedance.

For the signal path of a CMOS circuit to function correctly, a transmission design engineer must know how a driver behaves when driving a transmission line (usually 50 ohms). The driver must be able to drive this load at the desired rise and fall time.

The practice of testing driver rise and fall time using a capacitive load, such as 60 picofarads, rather than a 50- ohms transmission line, actually overloads the driver and results in an apparent rise time that is much slower than what it will be in an actual circuit. For a DDRAM array driver, this often results in a propagation delay difference in excess of 1 ns. This can cause timing errors.

These problems require a revamping of IC data sheets. Instead of output current ratings, output impedance at rated speed needs to be listed; instead of using capacitive loading to measure rise and fall times, they should be measured while driving a common transmission line impedance, such as 50 ohms; and worst-case Vcc and ground bounce must be stated. By adding an Ibis or Spice model of each input and output, a signal integrity engineer can design stable circuits.

A full discussion of this topic can be found in Chapter 48 of Right the First Time: A Practical Handbook on High Speed PCB and System Design, Volume 1).

Lee Ritchey is the founder and president of Speeding Edge(www.speedingedge.com), a consulting firm specializing in the high-speed pc-board and system design disciplines.