United Business Media EE Times


Search

HOMEMARKET INTELLIGENCE UNITFORUMSDESIGNNEW PRODUCTSCAREERSBLOGSCONTACTEVENTSSIGN UP!RSSMost Popular contentTrusted Sources

 


Software key to SoC design
Print this article Email this article Reprints RSS Digital Edition

EE Times


GOERING_RICHARDWe've all heard that logic verification has become the biggest single bottleneck for getting systems-on-chip out the door. That's true if we're looking at hardware design, but if we cast a broader net, the biggest bottleneck may turn out to be embedded-software development.

The Virtual Socket Interface Alliance (VSIA) recently set up a development working group (DWG) for "Hardware-dependent Software" (HdS). This includes drivers, boot code, hardware-dependent portions of protocol stacks, DSP algorithms and the like. In several eye-opening presentations at the recent Embedded Systems Conference, the motivations behind this effort became clear.

Tim O'Donnell, VSIA president, noted that when his organization began its efforts, 90 percent of the effort in developing an SoC went into hardware. Now, he said, it's typically a 50-50 split between hardware and software, with the balance shifting toward software.

Bob Payne, vice president and general manager of Philips Semiconductors' ASIC Systems group, showed a Moore's Law slide with a different twist. If you've attended an EDA-related conference in recent years, you've probably seen the slide that shows the 59 percent annual complexity growth predicted by Moore's Law vs. the 20 to 25 percent compound annual growth in design productivity. That 20 to 25 percent growth rate is for hardware design, however. Payne's slide showed software productivity growing at only 8 to 10 percent annually. With Philips SoC design teams today, Payne said, about half the effort goes into software and half into hardware. Over time, he predicted, more and more will go into software.

Michael Kaskowitz, head of the HdS DWG and vice president of Mentor Graphics' embedded systems division, said it's not uncommon to find two to five software designers for every ASIC hardware designer. With some SoC devices, he said, 70 to 80 percent of SoC development time may be spent in software development.

Standards for HdS reuse will help a lot, and for that reason, the DWG is working to define a hardware abstraction layer that will allow the creation of reusable software "virtual components."

The other part of the problem is cultural. Why is the EDA industry, which serves a much smaller clientele, five or six times larger than the embedded-software development-tools industry? Most companies don't assign equal value to hardware and software development. Those that start to do so will be the ones who get SoC devices out the door first.





The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


  Free Subscription to EE Times
First Name Last Name
Company Name Title
Email address
  Click here for your Free Subscription to EETimes Europe
 
CAREER CENTER
Looking for a new job?
SEARCH JOBS
SPONSOR

RECENT JOB POSTINGS
CAREER NEWS
SRC Expands R&D Centers
The Semiconductor Research Corp has added a new center to its university R&D efforts.

For more great jobs, career related news, features and services, please visit EETimes' Career Center.



All White Papers »   

  Design Resources
Designing for a dual Galileo-based GPS system
Malcolm Lomer of SiGe Semiconductor discusses GPS design challenges with the Galileo satellite system.
More »
 
Education and
Learning


Learn Now:












Home | About | Editorial Calendar | Feedback | Subscriptions | Newsletter | Media Kit | Contact | Reprints|  RSS|   Digital|  Mobile
Network Websites
International
Network Features




All materials on this site Copyright © 2009 TechInsights, a Division of United Business Media LLC All rights reserved.
Privacy Statement | Terms of Service | About