The largest and best-funded of these newcomers is AmmoCore (ammocore.com), which earlier this month announced Silicon Fabrix, a netlist-to-routing tool that claims to offer significant advantages over existing block-based tools. Its SuperFlat mode creates "tiles" of up to 10,000 or so standard cells, places them, runs optimization and routes most of the design. But it's not a complete routing solution, so you'll need Cadence Design Systems' Silicon Ensemble to finish the job.

Maybe the folks at AmmoCore should talk to the people at ViASIC (viasic.com), a small startup that's preparing a standalone router that can work with placement-plus-optimization tools. ViASIC has already developed gate array routing tools and is promising delivery of a standard-cell router that offers high capacity and fast performance for 0.13-micron-and-below designs.

Also in the IC layout space, Silicon Canvas (sicanvas.com) offers Laker, a full-custom layout editor that will compete with Cadence's Virtuoso offering. Laker claims to bring a new level of automation to custom layout. It includes a design browser, schematic generator, automatic transistor placer, floor planner, shape-based router and Magic Cell, which maps logical components into physical representations.

In the verification area, Tempus Fugit (tempusf.com) is preparing an interface protocol checker that claims to make formal techniques easy to use. TempusQuest, planned for release later this year, takes in RTL code and checks compliance for protocols such as PCI, AGP, USB, HyperTransport and many others.

Bridges2Silicon (bridges2silicon.com) has hardware and software that lets users debug logic in the target system, at full speed, with VHDL or Verilog source code support. It embeds debug logic into the design that samples internal signal values, and sends them off-chip for analysis and display.

Finally, EDAptive (edaptive.com) offers a tool set based on Rosetta, a system-level constraint language under development by the Accellera standards body. It includes a block diagram and constraints editor, an intellectual-property management tool, a partitioning tool and a test vector generator.

Some of these ideas will work better than others, but each company is bringing a fresh perspective to a complex problem. Let's not let the recession scare us into looking only at big EDA vendors.