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Decline in chip design?
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EE Times


GOERING_RICHARDI don't mean to spoil a nice summer's day, but I see signs that traditional ASIC and system-on-chip (SoC) hardware design may be heading for a decline. The high cost of chip design and manufacturing, coupled with what may be a lackluster demand for high-performance chips, may lead us away from solutions differentiated by custom hardware.

A July 1 EE Times article on page 1 notes that chip makers are coming to understand a new reality: Raw speed and performance don't sell like they used to. What OEM customers most want, the article notes, isn't big SRAMs, 500-MHz processor, or gazillions of gates; it's low costs. As a result, many chip makers are coming out with scaled-down, lower-performance, price-sensitive products.

As we all know, the cost of designing hardware for complex chips is escalating rapidly. And so is the cost of manufacturing, with 0.13-micron masks running at more than $700,000.

We also know that the electronics industry produced tons of expensive, sophisticated gear in 2000 and 2001 that nobody really wanted. That's what caused the technology stock market crash. When people show those Moore's Law PowerPoint slides and talk about how we'll be awash in 100-million-gate, 1-GHz chips by such-and-such date, they never consider an important question: Who really wants those chips, and will they go into products that companies, and people, will actually buy?

If cost is more important than capacity and performance, then hardware design, as we know it, may become too expensive. That means we may see more platform-based designs, and more programmable or software-oriented solutions, than we have in the past. We may also see a slower move to 0.13 micron, already delayed because of concerns about high mask costs and timing closure.

Dataquest's Gary Smith says that platform-based design does not work for SoC devices, because with a fixed architecture, you can't get a competitive advantage out of the silicon. But what if the issue is not crafting silicon for the highest possible performance, but designing a low-cost, "get by" solution in the shortest possible time? Then we shift more to an embedded methodology, where the differentiation is in software.

With every challenge comes new opportunities, and I'm sure design-for-cost will present a need for new tools and methodologies. But there may be some painful transitions in store for today's RTL silicon chip designers.





The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


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