EDA vendors seem to be viewing 90 nanometers as a significant turning point for design tools and methodologies. But the real shift may have more to do with the changing notion of "signoff" between design teams and fabricators. Notions about when signoff occurs, and what it includes, need radical revision for any sub-0.13-micron technology.

The traditional gate-level signoff approach is already falling apart. That approach separates synthesis from placement and routing-a split that doesn't work well below 0.18 micron. It forces too many iterations between ASIC vendors and design teams.

An alternative is "placement-based signoff" following physical synthesis. That gives better predictability, but still separates placement from routing and once again leads to iterations and unpleasant surprises.

I suspect that two signoff styles will become prevalent below 0.13 micron: RTL signoff and GDSII signoff. Many ASIC providers are accepting RTL signoffs today from selected customers. It's controversial, however. If the ASIC vendor doesn't have the RTL source and can't change it, that poses limitations and may result in a lot more phone calls than either side would like.

Many "power" users have already gone to GDSII signoff. That is, they do synthesis, placement and routing in-house, along with extraction, analysis and design-rule checking. They then go to a foundry, such as TSMC, rather than a full-service ASIC vendor. This is the way to go for ultimate control over a design, but many design teams don't have the required expertise.

Wherever it occurs, it's clear that signoff must include much more than just timing. There will also need to be "power signoff," not only for power dissipation but also for power grid analysis. "Reliability signoff" will examine the effects of IR drop and electromigration. "Signal integrity signoff" will certify that noise and crosstalk won't wreak havoc with delays and cause other unwanted effects.

"Testability signoff" is already in place today, but what's coming is "manufacturability signoff," which will account for process variations and help maximize yields.

For RTL signoff, an accurate silicon virtual prototype is essential. It must predict not only timing, but also power, signal integrity, reliability, testability and manufacturability. For GDSII signoff, the silicon virtual prototype can serve as a "cockpit" that guides the rest of the design process.

So the question isn't so much whether IR drop gets worse at 90 nm. It's what kind of signoff will get the best use out of the process.