Cadence Design Systems authors outlined that company's vision for unified verification last week in a white paper at www.EEdesign.com.

The idea is to start with a new type of tool, a "functional virtual prototype," that provides a high-level view of the entire design from a verification standpoint. Designers then use formal tools, HDL simulators, analog/mixed-signal simulators, accelerators and coverage tools on selected blocks as appropriate, all within a consistent user interface and testbench generation environment.

This vision is a good first attempt at what Gary Smith, chief EDA analyst at Dataquest, calls the intelligent testbench. Smith's concept adds partitioning capabilities that can help select the best strategy for each block.

Synopsys is thinking along similar lines. Sanjiv Kaul, senior vice president for corporate applications and marketing, recently predicted that tight integration of simulation, testbench creation, coverage and analysis tools will become "production ready" this year.

Also exciting, Kaul noted, is the "unification of design and verification languages" through the upcoming SystemVerilog 3.1. This language, which Accellera expects to release by June, includes testbench generation and assertion capabilities that leverage contributions from Synopsys' OpenVera.

But perhaps there are some more-basic priorities. When I asked several prominent EDA users for their "wish lists" late last year, two pointed to the lack of support for Verilog 2001.

"First on my wish list is that all EDA vendors implement Verilog 2001, and that they follow the LRM [language reference manual]," wrote Anders Nordstrom, senior ASIC engineer at Elliptic Semiconductor and a member of the IEEE 1364 Verilog standards committee. "If the EDA vendors can't even implement the [Verilog 2001] IEEE standard, I believe we are not going to see any consistency if they try to implement SystemVerilog."

"The EDA industry has been rather slow to change," wrote James Lee, president of consulting firm The ASIC Group. "Many EDA tools do not even support all the features of the [Verilog] 2001 standard."

Perhaps an "intelligent" approach to verification can start with better support for something that's here right now.