What major theme, or themes, will emerge at the Design Automation Conference in Anaheim, Calif., two weeks from now? I see several possibilities. One might be the rebirth of electronic system-level (ESL) design, another might be power management, and a third might be the dearth of Asian attendees due to the SARS virus.

ESL is an interesting theme to ponder because, 10 years ago at DAC, something called electronic system design automation (ESDA) was the rage. ESDA fizzled, along with most of the companies focused on it at the time. System-level design has been around for years and has never caught on.

But, now, as sub-100 nanometer geometries bring on 100 million-gate chips, ESL's time may have come. This week's announcements from Future Design Automation, Axis Systems and Summit Design point to activity in that area, as does last week's CoWare ConvergenSC announcement.

Power management, including leakage current, is emerging as a huge problem for sub-100-nm ICs. The DAC program reflects it, with a Monday tutorial, Tuesday panel and several technical sessions. I also expect some product announcements, including this week's Atrenta SpyGlass introduction.

Of course verification will be a hot topic at DAC-it always is. I expect some activity in the formal space, including Synopsys' Magellan announcement of last week and this week's coming out of Jasper Design Automation (formerly Tempus Fugit). SystemVerilog 3.1 is sure to prompt lively debate.

But, for some people, the big question will be-Where are all the Asian attendees? SARS cannot be good news for DAC, or for the global EDA industry. Perhaps the very technology that EDA has made possible will help researchers put a rapid end to this latest epidemic. And perhaps ESL, power management and better verification will give us a leg up on the next one.

Richard Goering is managing editor of Design Automation of EE Times.

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