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Times are tough for verification
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EE Times


GOERING_RICHARDWith the oft-quoted statistic that verification now consumes up to 70 percent of chip design resources, you might think that verification engineers would have some job security. But according to postings in a recent newsletter of the Verification Guild, verification engineers might be even worse off than design engineers.

In this e-mail newsletter, several people commented on a previous posting from an engineer who said he was unable to find a job, even though he has four years' experience. "Should I just quit this profession?" he asked.

One response was especially succinct: "Nobody can find a job. It's not just you."

"Your experience is not unusual," advised another commentator. "If you have another profession you can walk into that's financially viable, go for it." This person noted that many engineering jobs are being exported to other countries, such as India, China and the former Soviet Union.

Another commentator had some practical advice: Start a design or verification project on your own through the www.OpenCores.org Web site, complete the project and bring the documentation to your next job interview.

Perhaps most telling was the posting that included, as an example, a "help wanted" ad for a staff engineer to do ASIC verification. The ad specifically called for a design engineer and did not ask for verification experience.

"The implication is very clear," wrote the person who posted this example. "Any designer is qualified to do verification. Have you ever seen an ASIC design position for which they said that they wanted a verification background and not design? Conclusion: verification is a 'trap state.' "

If employers presume that all design engineers can do verification, but verification engineers can't do design, this downturn is going to prove to be very tough on some of the people who are most needed to get complex chips out the door.

Richard Goering is managing editor of Design Automation for EE Times.





The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


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