In researching an upcoming feature article, I asked EDA vendor representatives what "new paradigms" will be needed to design sub-100-nanometer ICs. I was surprised at the answer I received from Rajeev Madhavan, Magma Design Automation's CEO: silicon compilation.

Talk about an old paradigm! Silicon compilation appeared in the mid-1980s as a new methodology for automatically generating GDSII layout files from high-level, parameterized blocks. It never really caught on, and by 1990, the concept had been pretty much shelved as designers embraced HDLs and moved to RTL design.

So why silicon compilation now? According to Madhavan, there's a need to dramatically reduce the R&D costs associated with chip design. What's needed is a tool suite that can take RTL and automatically generate GDSII, while also handling all physical-implementation portions of the design process, including timing, power and signal integrity analysis.

The new concept of silicon compilation differs from the old, Madhavan said, in that it accepts a captured and verified RTL description rather than parameterized building blocks. It then uses existing synthesis, placement and routing engines, along with analysis tools, to generate the final GDSII.

Today's integrated IC implementation tool suites are heading in that direction, but they have a ways to go. "Magma is closer than other EDA suppliers, but we don't have a true silicon compiler solution today," Madhavan said. "We need to get there to make the EDA recovery a reality, and I intend to direct our technical resources toward achieving that goal."

If EDA vendors can bring new life to an old idea, and provide an automated solution for generating chip layouts, it could be a big step forward-so long as they learn from the lessons of the past. To read more, see Madhavan's EDA Views column at EEdesign this week.

http://www.eet.com