Recent announcements from two startups, MicroEDA and ChipMD, suggest that the wall between chip design and manufacturing may finally be coming down. But whether chip designers actually want that wall to go away is far from clear.

The current thinking of most chip design teams is that the job is done when the final GDSII files are completed. In reality, it is far from done. Somebody must check and modify images, run fracturing and generate MEBES files for mask-making. Right now, that "somebody" is a mask shop employee looking at a bunch of polygons with no idea of what they do.

MicroEDA's proposal is radical but simple; put verification, image modification and fracturing in the hands of the design team, with a forthcoming tool that promises to let designers skip GDSII entirely and work from a database such as OpenAccess. This approach could potentially save millions in mask costs-but will designers want to take on the added responsibility?

Another problem is that process variations become a serious issue at 90 nanometers and below, and yields will suffer if they aren't taken into account. That's why ChipMD has come out with DesignMD, a "deterministic yield optimization" tool that resizes transistors according to process statistics and operating conditions.

DesignMD is aimed at analog and mixed-signal designers. So, whether digital ASIC designers will want to deal with yield optimization is an open question.

Gary Smith, chief EDA analyst at Dataquest, believes that the manufacturing issues will be so daunting at 65 nanometers that most ASIC designers will sign off at the register-transfer level. Only power users and ASIC vendors will implement chip designs, Smith believes. The poet Robert Frost said, "something there is that doesn't love a wall." In this case, maybe there's something that does.

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