In my last column of the year, I often review the year's top EDA stories. This year I'm coming from a different angle and looking at how the world of chip design changed in 2003. The short answer is "profoundly."

This year, some designers moved from 0.18 micron to 0.13 micron, and a few braved the waters of 90 nanometers. With this downward trend, power management has become a major issue. Designers are grappling with IR drop, cross-coupling and leakage current challenges that didn't exist before.

EDA vendors are responding not only with point tools, but with IC implementation tool sets that provide RTL-to-GDSII solutions. Magma Design Automation made some market inroads in 2003, while Synopsys came out with its Galaxy platform and Cadence Design Systems fielded SoC Encounter.

If power isn't scary enough, the manufacturing issues that loom at 90 nm and below are downright terrifying. Designers are going to have to learn what "yield" is, and design to maximize it.

Verification challenges grew this year, and perhaps the biggest development in this area is SystemVerilog, a language that brings assertion and testbench capabilities into Verilog. With up to 70 percent of the design cycle taken up by verification, "design-for-verification" has become a new mantra.

Spurred by growing complexity, electronic system-level design startups and tools are emerging at a rapid rate. The question is whether chip designers, who have not flocked to these tools in the past, will feel differently when they try to put 100 million transistors on a 90-nm chip.

But perhaps the biggest question in chip design is the most basic: What kinds of chips will be designed in the future, and who will design them? We've heard that ASIC design starts are slowing and FPGA design starts increasing. Gate counts aren't going down, but it appears that FPGAs and structured ASICs may replace conventional ASICs in at least some applications. Meanwhile, for complex sub-100-nm ASICs, interest in RTL signoff is growing.

The biggest concern of all, for many North American designers, is whether their chip design jobs will stay at home or sail off to India or China. The challenge of chip design in 2004 is remaining competitive in a global market with lots of smart engineers.

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