A recent EE Times Netseminar, in which I took part, underlined the growing need for ASIC-like tools for complex FPGAs. The question is whether FPGA designers will actually pay for them.

Held Nov. 20, the Altera-sponsored Netseminar, "FPGA and EDA: Working Together," looked at the need for tools such as physical synthesis, formal verification, debugging and hardware/software codesign for FPGAs. Panelists argued that next-generation devices will require tools that were conceived for high-end ASICs.

The technical argument is sound. The problem is economics and culture. Recently, I attended a panel at the International Conference on Computer-Aided Design (ICCAD) in which an FPGA designer eloquently stated the need for faster simulation, physical synthesis, floorplanning and hardware/software co-verification. Then he said he expects FPGA vendor tools to be "free or almost free," and that any third-party tools "had better be low cost."

It's somewhat similar to the situation in embedded software design. Companies that won't hesitate to pay $100,000 for synthesis or $500,000 for IC placement and routing will have fits should a software developer ask for a $5,000 C-language compiler. Never mind that embedded software is as likely to hold up the project as hardware.

So how to change the mind-set that FPGA tools should be free? "People will pay for tools so long as they yield real dollar savings in production," said Ken McElvain, Synplicity CTO. Tim Southgate, vice president of software and tools marketing at Altera, noted that many ASIC designers are now becoming FPGA designers. Hopefully for the EDA vendors, they will bring their big budgets with them.

Simon Bloch, general manager for Mentor's design creation division, said customers are complementing their FPGA vendor tool sets with commercial tools to help with high-end devices. He said FPGA design seats are averaging $10,000 now, but that this could rise to $20,000 or $30,000, still much less than ASIC design seats.

Add up the low prices, the technology demands and the need for automation and ease of use, and FPGA design is one of the most challenging areas of the EDA industry.

To access EE Times Netseminars, see http://www.eet.com/netseminar.html.

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