Accellera bypassed the IEEE 1364 group that's been responsible for standardizing Verilog to go with a new working group under the IEEE's Corporate Advisory Group (CAG). The proclaimed reason is that the CAG's "one company, one vote" policy will yield a faster standard. But given that the IEEE 1364 group also offered to consider such a policy, there's more to the story.

Despite a generally cooperative engineering effort, the SystemVerilog process has been rife with EDA vendor politics from the beginning. Synopsys contributed most of the technology and emerged as SystemVerilog's strongest backer, alienating competitors such as Cadence Design Systems and Verisity.

When Accellera last year declined to donate SystemVerilog to the IEEE 1364 group, that group solicited other contributions for its new effort, Verilog 2005. Cadence and Verisity stepped forward. Two vendor "camps" coalesced: Synopsys and Mentor backed Accellera; Cadence and Verisity backed the IEEE 1364 group, whose chairman, Mike McNamara, is a Verisity vice president.

Bowing to the growing momentum of SystemVerilog, Cadence and Verisity got religion and recently proposed a phased implementation through a "SystemVerilog implementation working group." From the view of Synopsys and Mentor, it's a "wait so we can catch up to you" effort. Five EDA vendors supporting the new group are having a Design Automation Conference event Monday, while the Accellera crowd has its SystemVerilog event Tuesday.

In the past year, Accellera's SystemVerilog committee worked pretty harmoniously with the IEEE 1364, whose Verilog 2005 is by now mostly drawn from SystemVerilog. The two groups share common members. But vendor politics apparently prevailed, and with the support of Synopsys and Mentor, Accellera wrested control of SystemVerilog from the IEEE 1364 group.

Now it is up to users to insist that IEEE 1364-2005 and IEEE 1800 SystemVerilog not end up as incompatible language versions.

Richard Goering is managing editor of Design Automation for EE Times.