EE Times this year ran customer surveys for IC, FPGA and pc-board design. The results were released at last week's Design Automation Conference. Of the 662 respondents to the chip design survey, 47 percent were design engineers, 28 percent engineering managers, 7 percent verification engineers and 5 percent CAD managers.

Asked about the time devoted to each design stage, system-level design came in at 13 percent; logic design at 20 percent; functional verification, 22 percent; synthesis, 8 percent; IC place and route, 13 percent; IC physical verification and analysis, 11 percent; and analog/mixed-signal design, 13 percent.

Twenty-two percent is a far cry from 70 percent. So where did that 70 percent figure come from? It shows, I think, that it's easy to throw around a vague statistic to make a point, and if enough people hear it enough times, no one questions it.

We might ask, 70 percent of what? Looking only at the RTL design phase, then perhaps functional verification might take half the effort, or more. But if we look at the entire design cycle, from the time system architects first start coding C models to the final GDSII tapeout, there would be a different story.

More to the point, I think, is this figure: The median design cycle has gone from 32 weeks in the 2003 user survey to 40 weeks this year. Thirty-eight percent of chip design efforts take one to two years.

During this same period, the median gate count rose from 1 million to 2 million. What happens when the median gate count is 10 million? How long will it take to put 100 million gates on a chip, as allowed by 90-nanometer technology?

The industry needs to do much more than make simulators run faster. We need new silicon architectures and new methodologies that bypass much of today's design cycle, and provide easier paths to silicon.

Richard Goering is managing editor of Design Automation for EE Times.