The 970-page Design Automation Conference proceedings for 2004 probably aren't at the top of your summer reading list, but they do offer insights into R&D work under way at design automation vendors. While most of the papers come from academia, a few reveal vendor research that may someday show up in products.

Marketing tomes don't make it into the DAC proceedings. This year, 163 papers were accepted out of 785 submitted. Those accepted are peer-reviewed, technical papers that describe the cutting edge of design automation research. Along with academics and EDA vendors, user companies like Broadcom, Cisco, IBM and Intel were among the contributors.

Synopsys Inc. presented several papers, including one that shows an interest in structured ASICs. It outlines a design auto-mation flow for "mask-programmable fabrics," a structured form of standard-cell design. The flow includes a new mask-programmable router that understands programmable routing constructs and a tool that packs logic efficiently after synthesis.

Another Synopsys paper describes a new abstraction refinement algorithm for formal property verification. It's said to outperform existing algorithms in terms of run-time, abstraction efficiency and number of proven properties.

Cadence Design Systems Inc. authors describe a "desynchronization" approach that lets a synchronous specification coexist with a robust asynchronous implementation. It describes clustering and temporal analysis techniques that decrease the overhead of desynchronization. In another paper, Cadence authors outline a new table-modeling technology that claims improved accuracy for Spice simulators.

One CoWare Inc. paper outlines "IP-driven" and "design-driven" approaches to application-specific, heterogeneous multiprocessor systems-on-chip. Another describes the Lisa 2.0 modeling language for application-specific instruction-set processors.

And startup Zenasis Technologies Inc. describes a technique that estimates cell layout characteristics without actually performing layout and extraction. It claims timing accuracy within 1.5 percent of post-layout timing.

It's a long route from a research paper to a production-ready EDA tool that's used for real tapeouts, but everything you're using today started with research. While academia will remain the primary source for original EDA research, it's encouraging to note that EDA vendors haven't given up on R&D.

The DAC proceedings are available at www.dac.com.

Richard Goering is managing editor of Design Automation for EE Times.