The first point to consider is that "consumer" does not necessarily mean "high volume." According to Charles DiLisio, president of consulting firm D-Side Advisors, only one of five consumer products makes it to market. Of those, only one of 10 reaches volumes of a million or more units. Further, OEMs practice "al dente" marketing, throwing out products with different feature sets to see what sticks.

It may cost $15 million to $20 million to design a custom ASIC, an expensive proposition for startups and small companies. As feature sizes drop below 130 nanometers, ASIC design requires increasingly expensive tooling, larger design teams and attention to challenges like signal integrity, leakage current and design-for-manufacturability.

Thus, for many consumer OEMs, ASICs are not the answer. Cheap consumer products, especially out of Asia, might well involve off-the-shelf ICs thrown onto a pc board, with differentiation in embedded software.

For many designs where functionality goes into silicon, FPGAs are a good, low-risk place to start. If high volumes kick in down the road, one can always go into an ASIC. These days, the choice might be a structured ASIC, in which some of the layers are prefabricated and an RTL-to-GDSII tool set is generally not required.

There are also a host of alternative programmable architectures to consider, such as those from Quicksilver, Stretch, Elixent and Tensilica. Many of these come with C-language tools that let users bypass conventional RTL ASIC design.

Another way to get into silicon is to use one of the new "algorithmic synthesis" tools. Synfora, for instance, has an "algorithm-to-tapeout" tool that places computationally intensive C algorithms into silicon.

Conventional ASIC design is just one way to get a product out the door. For very high volumes, very fast speeds or very small die sizes, it can't be beat. But applications that don't need these features have other alternatives. The EDA industry should not focus all its efforts on custom ASIC design.

Richard Goering is managing editor of Design Automation for EE Times.