Indeed, EDA has become somewhat of a stodgy industry, with flat revenue growth and an unclear sense of direction. What can cut through the malaise and bring back some excitement?

Finding the "next big thing" would help. Some think it's design for manufacturability, but the reality is that most designers don't want to deal with it. EDA gadfly John Cooley recently said that DFM stands for "dollars for marketing." Most industry observers wouldn't agree, but somehow the need to put resolution enhancement technology on more metal layers doesn't engender a lot of excitement.

Others think electronic system-level design is the big new thing. But ESL, under various names, has been around for more than 10 years, and in that time has had limited success. My guess is that few chip designers today could define what ESL is, and among those that think they can, the definitions would all be different.

Gone are the glory days of EDA, when HDLs and synthesis revolutionized chip design and put complex ASICs within the reach of thousands of designers. Now we've reached a point where the problems of 90- and 65-nanometer design are so daunting that fewer and fewer companies will even attempt the RTL-to-GDSII design flow.

What can be done? First, I think the EDA industry leaders need to articulate a clear, consistent vision of where we're going from here, if we are indeed moving beyond today's RTL design methodology. Second, get out of the ASIC "ghetto" and acknowledge the growing number of silicon alternatives, including structured ASICs, complex FPGAs and configurable logic.

How about this for a vision? Let me design a 100 million-gate, 65-nm chip at a high level of abstraction, refine it to RTL and hand it off to an ASIC vendor or automated tool suite. Let the resulting chip have good performance and cost efficiency, and come out faster than my last 130- or 90-nm design. Now that's exciting! Make that happen and EDA's vision problem will vanish.

Richard Goering is managing editor of Design Automation for EE Times.