Third-quarter reports won't be in until later this week, but already the predictions are disappointing. Magma Design Automation has cut its bookings estimates in half, citing delays in purchasing decisions and cautious customer spending.

Similarly, Synopsys has downgraded its quarterly and annual revenue and bookings forecasts, also citing increased caution by customers about spending money. It may see as much as a 27 percent year-to-year revenue decline in its fourth fiscal quarter, ending Oct. 13.

Yes, customers are cautious, but that's not the whole story. Another issue is that the move to 90 nanometers does not demand a wholesale retooling. It does require some new capabilities in signal integrity and power analysis, but not a whole new design flow. Electronic system-level tools may be needed to design the 100 million gates theoretically allowed by 90-nm silicon, but ESL revenues are ramping up slowly.

With yield, process and silicon issues, 65 nm will require retooling. But 65-nm design may be so tough that many ASIC designers will move to RTL signoff, resulting in fewer seats for RTL-to-GDSII implementation tools. Others will turn to FPGAs, structured ASICs or other silicon alternatives that don't need expensive tools.

If EDA vendors continue to focus on design tools alone, it's going to be tough to build large and growing companies. The way to expand the market is to look beyond tools and consider all that it takes to enable next-generation electronic designs.

That broader picture includes services, silicon architectures and intellectual property (IP). Consider: Synopsys tried to purchase embedded-memory IP provider MoSys, Cadence recently signed an IP development deal with Rambus and ARM bought Artisan. Perhaps "electronic design enabling" would be a better term than "electronic design automation."

Richard Goering is managing editor of Design Automation for EE Times.