This chapter covers the effect that package parasitic inductance has on the performance of high-speed logic circuits. Specifically, the package parasitic involved in this case is the unwanted inductance in the power paths into and out of an IC package. As logic speeds have increased and data and address buses have become increasingly wider, the noise spikes created by the current transients involved in these switching events have become a major source of failure.

Vcc and ground bounce are the shift in the Vcc and ground rails on the IC die with respect to their respective levels on the planes of the PCB. This type of unwanted transient is most often the result of single-ended logic drivers charging and discharging transmission lines. Figure 38.1 illustrates the way in which Vcc and ground bounce are created.

Figure 38.1 — A Typical Single Ended Transmission Line Showing Vcc and Ground Bounce

The left side of Figure 38.1 shows the current path for the current required to charge up the parasitic capacitance of the transmission line and the parasitic capacitance of the loads as the transmission line is switched from a logic 0 to a 1. The right hand side of Figure 38.1 shows the current path associated with discharging the parasitic capacitance as the logic line switches from logic 1 to a 0. These transient currents are the primary source of simultaneous switching noise (SSN). The inductance shown in the diagram includes the inductance of the vias that connect the IC power leads to the power planes.

Notice that the Vcc terminal of the IC die is driven negative with respect to Vcc on the PCB power plane during a logic 0 to 1 transition. All of the terminals of the IC are driven negative at the same time (this is Vcc bounce). The effect is that this voltage spike appears on all quiet outputs and inputs. If the spike is large enough, it can cause a logic failure. During a transition from logic 1 to 0, the ground rail of the IC is driven positive with respect to ground on the PCB power plane (this is ground bounce). This spike appears on all lines as well and can cause logic failures.

Equation 38.1 can be used to calculate the magnitude of the voltage transient that results from a change in logic states.

Equation 38.1 — An Equation for Calculating the Voltage Drop Across an Inductor

Where: VL = the voltage drop across the inductor, L is the inductance of the inductor in Henrys, di = the magnitude of the change in current in amps, dt = the time required to make the current change.

Notice that voltage drops occur across inductors only when the current through them is changing or, more precisely, when the electromagnetic field traveling through them is changing.

Table 38.1 lists the lead inductances of some typical IC packages. The reason for the wide spread in inductance is the fact that the leads in most packages are of widely different lengths.

Table 38.1 — Typical Lead Inductances of a Variety of IC Packages

To get some sense for the magnitude of Vcc and ground bounce that can occur in a common IC package, a simple calculation can be done. As an example, the 20 pin DIP (dual in line package) will be used. The power pins on this package are on the corners and have an inductance of 13.7 nanoHenries per power pin. The delta I in this case is when the logic state changes from 0 to 1 is 50 mA for a single output and the delta time is 2 ns for a 5V HCMOS part. Using these values in equation 38.1 results in a voltage spike of 342 mV.

Imagine what happens when all 8 bits of a bus are changing simultaneously from 0 to 1. The voltage spike is 2.74 Volts. Next, the rise time is changed to 1 ns. The spike is 5.48 Volts. It is switching transients such as this that drove the change from DIP to PLCC packages. Companies that attempted to increase logic speeds while remaining in the tried and true packages found that their products did not work properly. It should be noted that this problem is package related and cannot be fixed by actions taken on the PCB.

Vcc and ground bounce (SSN) are caused by excessive inductance in the power paths of IC packages. No actions on the PCB can be taken to fix this problem. Changing to an IC package with lower package lead inductance is necessary.

Failure to understand that this phenomenon is at work leads to designs that are never stable. Because of this potential failure mechanism, it is imperative that each part being considered as a driver of a single-ended logic bus be checked out prior to being used in order to insure SSN does not cause failures. Figure 38.2 illustrates a test setup used to measure worst-case SSN.

Figure 38.2 — A Test Setup For Measuring Worst-Case Vcc and Ground Bounce

In order to measure worst-case Vcc and ground bounce, it is necessary to load all of the outputs of the widest bus with a realistic set of loads that can switch simultaneously. It is common to test IC outputs by attaching a large capacitor, for example 60 pF, to each output and observe the rise and fall time. This is not a realistic load. It "overloads" the output and results in a rise or fall time that is slower than will actually occur when the output drives a transmission line. In addition, the current spike needed to charge up or discharge the capacitor is much larger than will occur in actual use. A realistic load is a 50 ohm transmission line as this is what the part will usually be expected to drive.

In Figure 38.2, all of the outputs are "loaded" with 50 ohm transmission lines. The measurement probe is connected to an output that is powered from the same internal power and ground bus as the data lines that will be switched. The IC is mounted on a PCB with a power plane structure that is capable of supplying the charging currents needed to switch all of the data lines from 0 to 1 simultaneously without drooping.

To observe Vcc bounce, the IC is driven with a signal pattern that will cause all of the data lines to switch from 0 to 1 simultaneously. While this is happening, the Vcc bounce associated with this event will appear on the quiet line with little or no attenuation. The Vcc bounce waveform results from the rising edge of this current waveform.

To observe ground bounce, the IC is driven with a signal pattern that will cause all of the data lines to switch from 1 to 0 simultaneously. While this is happening, the ground bounce associated with this event will appear on the quiet line with no attenuation.

The waveforms in Figure 38.3 are measured in this manner on an actual IC. In this case, the data bus being switched is 64 bits wide and the Vcc is 2.5 Volts. The top trace is a combination of Vcc and ground bounce. The excursions above Vcc are ground bounce and the excursions below Vcc are Vcc bounce. This set of waveforms was produced by toggling all of the data lines from 0 to 1 and then 1 to 0 many times.

Notice that the excursions are about the same amplitude, 500 mV. From this it can be inferred that the inductance in both the Vcc and ground paths are about the same size. It is possible to get a rough idea how big this inductance is. This is accomplished by using equation 38.1.

The peak current per output is 2.5V/100 ohms or 25 mA. The total current is 64 x 25 mA or 1.6A. The resulting voltage is 0.5 V. The delta time is 2 ns. The inductance is calculated to be approximately .625 nH. This inductance is a combination of the inductance of the IC package leads and the vias reaching down into the PCB to access the power and ground planes.

From earlier power supply discussions, it has been established that the current needed to perform this switching function is drawn from the plane capacitance built into the PCB. If this capacitance is not large enough, there will be ripple on Vcc every time the data lines switch from 0 to 1. This is shown in the upper left hand corner of Figure 38.1 as a "v" shaped dip.

The lower waveform in Figure 38.3 is the ripple on Vcc that corresponds to these switching events. In this example, the plane capacitor that was designed into the PCB to support this event was 24 nF. The resulting ripple is approximately 150 mV. For 2.5V logic, this is near the limit of what is acceptable. The only way to reduce this ripple is to redesign the PCB stackup to add more plane capacitance. Discrete capacitors have too much inductance to solve this problem.

Figure 38.3 — Actual Vcc and Ground Bounce on a 64 Bit Data Bus with Vcc Noise Shown

In addition to designing the PCB stackup to produce enough plane capacitance to supply the switching transients, it is important to minimize the inductance of the vias required to reach the planes. Therefore, the plane pair that supports the largest data buses should be the first plane pair below the components.

The waveform in Figure 38.3 is the power on reset line for this particular design. Each time all members of this data bus switched from 0 to 1, the system went through a power on reset cycle. This would happen during a memory access. The result was a system that could not be shipped and could not be fixed by taking any action on the PCB. The only remedy was to redesign the IC package. Such designs are often called Silicon Valley Tombstones.

Figure 38.4 — Actual Vcc Bounce on a 80 Bit Data Bus with Vcc Noise Shown

Figure 38.4 is the Vcc bounce waveform from another IC with an 80-bit data bus switching from 0 to 1 simultaneously. Also shown is the noise on Vcc. It should be noted that the Vcc noise related to this switching event is so small that it is difficult to see. This is because the plane capacitor that supports this switching event is 140 nF or seven times that in Figure 38.3.

The Vcc bounce in Figure 38.4 is from a 2.5V DDR data bus. The effective inductance that caused this noise can be calculated using Equation 38.1. In this case, the delta I per line is again 25 mA. The total delta I is 2A. The delta V is 216 mV. The delta T is 1.15 ns. From this, the equivalent L is 0.497 nH. Again, this is a combination of the package inductance and the inductance of the vias that connect to the power planes.

The example in Figure 38.4 has a relatively slow rise time of 1.16 ns. The component in this example is capable of producing rise times of less than 0.5 ns. Should one of these parts on the fast side of the performance spectrum be mounted in the same circuit, the Vcc bounce would be twice that shown, or 532 mV. This would be far in excess of the noise tolerance of this circuit. Redesigning the package to reduce the parasitic inductance is the surest way to fix this problem.

If redesigning the IC package is not a choice is there any other possible solution? In some cases there is. The source of the noise problem is many outputs switching simultaneously. Sometimes it is possible to stagger the clocking of the outputs such that only a portion can switch at the same time. This is often called a multiphase clock. Yet another choice might be to distribute the outputs on several Vcc and ground rails. This is possible with some of the FPGAs on the market.

One of the parameters in this equation is the rise time of the signal edge. It might be possible to slow down the edges.

Of course, the best solution is to select components that have packages with very low inductances in the power and ground rails. Table 38.2 shows the amount of Vcc or ground bounce that a variety of 2.5V wide data buses will create for 0.5 nSEC edges as a function of the total inductance in the power path.

Table 38.2 — Vcc and Ground Bounce vs. Package Inductance, 2.5V CMOS, 0.5 ns Edge

As edges get faster and data buses become wider, the design of the IC package must be done with great care if failures from Vcc and ground bounce are to be avoided.

Every IC that is intended to drive a wide data bus must be checked to insure the package inductance is low enough to produce acceptably low Vcc and ground bounce.

It is unwise to include a part in a design for which the vendor is not able to demonstrate Vcc and ground bounce numbers.

How to determine Vcc and ground bounce for new ICs prior to their being packaged

Often, it is necessary to choose a part while it is still in development. There isn't a real part to measure. It is possible to model the I/O and package in a Spice modeling software package and calculate the anticipated Vcc and Ground bounce. This is done by obtaining a Spice model of the output driver, combining it with the predicted inductance of the package power and ground paths, driving transmission lines of the appropriate impedance and switching the outputs at the fastest rise and fall times expected in the final circuit.

Examples of poorly designed BGA packages

In general, BGA packages have better Vcc and ground inductances than do other package types, such as QFP, PLCC and DIP. However, this is not always so. Some BGA packages are designed such that there are leads or wires from the power and ground contacts out to the balls that contact the PCB. When a new component in a BGA package is being considered, it is imperative that the package layout be examined to insure both Vcc and ground paths have low and equal inductances.

Figure 38.5 is a photograph of two two-layer BGA packages with this problem. In both cases the die is mounted in the cavity over contacts that pass directly through the package to balls on the backside of the BGA. These are the ground contacts and are very low inductance. In both cases, the Vcc leads are traces that travel from the edge of the die to the edge of the BGA package as traces.

Figure 38.5 — Two BGA Packages That Have Excessively High Inductance in the Vcc Leads

Determining what is an acceptable amount of Vcc and ground bounce

The amount of Vcc and ground bounce that can be tolerated is calculated by analyzing the noise from other sources and comparing it to the noise margin for the logic family being used. A portion of the total noise margin can be consumed by Vcc and ground bounce. The methodology used to perform this analysis is presented in subsequent chapters.

Lee Ritchey is founder and president of Speeding Edge, which offers private, on-site training classes to high-tech companies as well as courses through U.C. Berkeley's extension program and industry conferences.