The founding team at the Santa Clara, Calif., company includes four engineers who worked together on electrical timing signoff and developed the effective-current-source model (ECSM) now undergoing standardization at the Silicon Integration Initiative, said Jun Li, Anova's founder, president and CEO.

Today, Anova has a working product and a customer relationship with Fujitsu Ltd., which is using Anova's variation analysis and characterization technology.

Li and the other founders of Anova developed the ECSM model in 1999 at Altius Solutions, which was then acquired by Simplex Solutions, which in turn was acquired by Cadence Design Systems Inc. Li left Cadence in 2003 to run a physical verification startup, ETOP, that was acquired by Cadence in 2004. After that, Li spent time reviewing upcoming challenges in IC design and concluded that variability was the issue that stood out.

Li launched Anova in May 2005. Ping Chao, a founder of Cadence and Silicon Perspective Corp., sits on Anova's board, as does Hiroyoshi Usuda, former CFO of Japanese EDA distributor Innotech.

"The next big thing for signoff is variability and design-for-yield," Li said. "We want to come up with technology to help the customer analyze the variation, then move on to help customers optimize designs and help them get better parametric yield."

As such, the company could be considered to be yet another design-for-manufacturability startup, but Anova is a different breed, Li said. "Most DFM guys are working on OPC [optical proximity correction], but I still don't believe the designer has to do OPC in the future," he said. "I do believe that variability has to be addressed in design."

The Anova Suite has three "levels" of solutions. First is a process variation analysis technology, delivered to Fujitsu in December. It captures variations by running an analysis based on measured electrical data from test chips. As such, it's a tool for IDMs or foundries. The current focus, said Li, is on device variations, such as transistor length and width, as well as geometric concerns such as critical-dimension (CD) variations.

The second level is stochastic model-generation, delivered to Fujitsu in April. This is essentially a cell library characterization tool that produces statistical timing models. It creates what Anova calls a "unified variation model," which considers transistor and CD variations to predict cell timing, performance and leakage.

Generating these models is time-consuming, and Anova has developed a characterization methodology that's flexible and fast, Li said. In that respect, Anova may be competing against Altos Design Automation Inc., a startup that last week said it will provide a cell characterization capability for statistical analysis (see July 3, page 1).

The first two levels of the Anova suite are available now. The third level, to be rolled out in the fourth quarter, is "variation aware" timing analysis.

This timing analysis will include both static and statistical timing capabilities, Li said. In that respect, Anova will compete with other providers of statistical timing analysis tools, but Li said his company is different because of its "bottom up" approach: "We are not just providing a static or statistical timing analysis tool; we are providing an entire flow."

Looking ahead, Anova plans to go beyond timing. "Power is next year's issue," Li said. "We believe the same [variation] technology can be applied to power and leakage analysis, but we have limited resources, so we're focusing on timing."

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