SUNNYVALE, Calif. — Taiwan Semiconductor Manufacturing Corp. unveiled the latest version of its design-for-manufacturing (DFM) EDA tools and data kit for 65-nm chip designs on Monday (July 17).

The tool suite, referred to as Reference Flow 7.0, adds statistical timing analyis, enhanced power management capabilities and enhanced DFM features to the set of features already available in its previous release. The new suite also adds a Magma Design Automation's implementation track to the existing Synopsys and Cadence design tracks to broaden the adoption options for TSMC's 65-nm process technology.

The reference flow also incorporates a DFM unified format as the foundation for TSMC's tool compliance program. TSMC and its partners have run multiple compliance tests to validate interoperability between the format and the Ecosystem partner tools, said Ed Wan, senior director of design services product marketing at TSMC. This ensures that designers can use the tools and models offered by TSMC and its partners and use TSMC's process-specific, encrypted DFM data kit.

The inclusion of statistical timing analysis in the reference flow allows designers to optimize design margins and chip yields by analyzing the timing efforts of manufacturing process variations. Such variations can affect timing closure. Hence, new tools and methodologies are needed to predict circuit performance, Wan said.

Designers can also analyze the process variance impact on timing. This can be applied to statistical SPICE models, library and intellectual property characterization, standard-cell design kits, EDA tool enhancements and related design methodologies.

With power a growing concern, power management support in Reference Flow 7.0 provides dynamic and leakage power reduction tools. Dynamic power reduction enhancements include an improved voltage-island implementation and multicorner timing closure. A coarse-grained power gating technique helps achieve leakage reduction of up to two orders of magnitude.

Along with power management libraries such as isolation cells and data-retention flip flops, the reference flow adds a new level-shifter cell that is 50 percent smaller than previous cells and a coarse-grained power gating switching cell designed to prevent electromigration, minimize voltage drop and ensure fast wake-up time.

To ensure designs can be manufactured, the enhanced DFM features add critical-area analysis to help identify random manufacturing defects caused by conducting or nonconducting particles. The tool also drives wire spreading and widening to improve manufacturability.

Another tool, virtual chemical-mechanical polishing analysis identifies metal and dielectric thickness variation hot spots and guides dummy metal insertion to improve thickness uniformity throughout the chip. Additionally, various lithography process check post-production tools have been qualified by TSMC as DFM-compliant.