An HDL to HTML translator, HDL2HTML, is available as a free download from design services firm Millogic.

The goal of the Leox Project is to provide a complete, free, open-source set of hardware and software components that can be used to build an embedded computer that can be incorporated inside an ASIC or FPGA.

Project VeriPage is a site that promotes Verilog PLI usage. It includes a FAQ, free examples, and a tutorial for beginners.

The Open Verification Library (OVL) provides a set of Verilog assertion monitors that have been donated to Accellera, and can be downloaded for free

The OpenVera web site provides information about Vera, a testbench generation language available on an open-source basis from Synopsys.

TestBuilder is an open-source C++ class library for testbench generation developed by Cadence Design Systems.

The Open Cores site coordinates projects aimed at providing open-source silicon intellectual property (IP) blocks.

OpenTech is a distribution package for open-source EDA tools and hardware designs.

OpenSupport Partners is a program that provides support for users of open-source EDA tools and hardware.

Synopsys' TAP-in makes widely used interoperability formats and reference implementations immediately available to EDA developers and users.

The Linux EDA site provides a listing of vendors and products offering tools on Linux platforms.

Open EDA is a new web site from the Silicon Integration Initiative (Si2) that provides open-source licensing for EDA standards.

The Open Collector now hosted by SEUL (Simple End-User LInux), provides a comprehensive list of open-source and GNU Public License (GPL) EDA tools.

The FreeHDL Project is working to develop an open-source VHDL simulator for Linux.

The FreeIP Project is an effort to make silicon IP widely available, and it offers several free cores.

The gEDA Project offers a mature suite of open-source applications for electronics design, including schematic capture, attribute management, BOM generation, netlisting into over 20 netlist formats, analog and digital simulation, and PCB layout.

SystemC is an industry initiative, led by Synopsys and CoWare, that offers a C++ modeling platform through open community licensing.

CynLib is an open-source C++ class library offered by CynApps.

The Free Model Foundry, previously known as the Free Model Foundation, offers open-source Verilog, VHDL and IBIS models.

V-2000 is a project to develop a freeware Verilog, VHDL and mixed-signal simulator.

U.C. Berkeley's Polis Project offers a framework for hardware/software codesign of embedded systems.

Open-Source EDA Tools

You can create Verilog test benches in the Ruby language with Ruby-VPI, which provides an interface to the Verilog Programming Language Interface (PLI).

VeriWell, a full Verilog simulator that was previously a commercial offering from Wellspring Solutions, is now available on an open-source basis.

The Register Description Language (RDL) developed by Cisco Systems lets engineers describe control registers at a high level of abstraction.

RASP is an FPGA/CPLD technology mapping and synthesis package developed at the UCLA VLSI CAD lab.

ESys.NET is a new system-level modeling and simulation environment that takes advantages of .NET capabilities such as introspection and multi-lingual model definition.

With MyHDL, you can use Python as a hardware description and verification language, and you can convert implementation-oriented MyHDL code to Verilog automatically.

Jove is a set of Java APIs and tools that allow for the Verilog verification of ASICs and FPGAs using the Java programming language.

An open-source "Bookshelf for fundamental CAD algorithms" is available to academia and industry.

Academic physical design tools including the Capo placer, Parquet floorplanner, and MLPart partitioner are available at this University of Michigan web site.

Jeda is a Java-based HDL developed at Brigham Young University for high-performance FPGA design.

Dinotrace is a free waveform viewer for Linux and Windows.

Verilator is a free high-performance simulator that translates Verilog to C++ or SystemC.

GHDL is a free VHDL compiler that serves as a front-end to the GCC compiler suite, with no intermediate conversion to C/C++.

cdsp4 links Cadence Design Systems layout tools to Perforceýs data management tools.

A free VHDL to Verilog translator is available from Australian silicon IP provider Ocean Logic.

ASIC designer Chuck Benz created csrGen, a Perl script that automatically creates the control status register that handle processor read/write access in ASIC or FPGA designs.

Utilities at this U.C. Berkeley site let you link scripting languages such as Perl, Python and Tcl to EDA tools.

RHDL is a Ruby-based HDL created by engineer Phil Tomson. It's available under GPL at this site.

A lint package for C/C++ is available at the Splint (Secure Programming Lint) web site.

The web site for "Principles of Verifiable RTL Design" has a link to an open-source lint tool evaluation script

Source Navigator for Verilog is a development environment useful for navigating large design projects with many scattered files.

Alliance is a complete set of free CAD tools and portable libraries for VLSI design, developed by the Pierre et Marie Curie University in Paris, France.

nEwhere is an electronic design collaboration tool from Novas Software based on a GPL utility.

Vaul is a VHDL analyzer and utility library from the University of Dortmund, Germany

Savant is an extensible, intermediate form for VHDL developed by the University of Cincinatti.

Icarus Verilog is a synthesis and simulation tool that runs on multiple operating systems.

The Electric VLSI Design System is a GPL-based product offering schematic capture, simulation, and IC layout.

Magic, the classic ASIC layout tool developed at the University of California at Berkeley, is still available as an open-source product.

Thud, an RTL simulation environment optimized for cycle-based design, uses a Scheme-based HDL.

Michael McNamara, founder of Surefire Design Automation, offers Mac's Verilog Mode for emacs, a GPL Verilog editor.

vIDE is a cross-platform, integrated environment for designing, debugging and testing Verilog applications, available under GPL.

The OpenMore program launched by Synopsys and Mentor Graphics offers a downloadable program for scoring IP reuse.

Ver, a structured Verilog compiler, is intended to overcome the source-code size limits of the VeriWell training simulator.

F-CPU project is a on-line community developing a fully SIMD superpipelined, GPL'd CPU for 64-bit and larger platforms. Its sources are distributed under the terms of the GNU licence supplemented by a charter. You can think about it like the "Linux of the CPU world"

Written by a chip designer, ChipVault lets users launch synthesis tools, track VHDL and Verilog files, and navigate hierarchy.

Jeda is a C-like verification language written by a verification engineer.

To suggest additions to this list, e-mail Rich Goering .