Another emerging critical issue due to technology scaling is the effect of on-die temperature variation. What was previously a second-order effect that could be adequately addressed with a few corner cases and guardbands has now become a first-order effect. It interacts with a number of these other issues in ways that make analysis difficult. There's a need for new, temperature-aware design methodologies in order to produce properly functioning and reliable first silicon.

For the first time, local chip temperatures are driving overall design methodologies and power management schemes. The magnitude and complexity of this temperature-power relationship has created within the design community a sense of urgency to address temperature issues. Temperature values within a chip are a function of the materials, their dimensions, package characteristics, and ambient conditions. The high concentration of power in today's designs results in the self-heating of devices and interconnects, leading to larger temperature variations within the chip.

In digital circuits, temperature can vary as much as 50C across the die, and even higher in the metal layers. Digital designers now have to be concerned about heat and temperature gradients. This paper addresses the various issues arising from temperature gradients and their effects on the electrical characteristics of digital designs.

Today's digital design methodologies assume a constant temperature across the chip for analysis of the electrical characteristics. All devices and interconnects are considered to be at the same temperature, and several temperature corners are analyzed with global de-rating factors to verify circuit operations and detect any violations.

But in reality, for a given combination of power density of the devices and power dissipation on the metal lines, the temperature variation within the chip is far from uniform, and it makes the first order, constant-temperature plus guardband analyses suspect.

It is difficult to predict the chip temperature profile from its power density or power distribution. Careful temperature profiling has shown that the regions with the maximum power density on the chip or the maximum power value usually do not correspond to the region with the maximum temperature.

The power distribution and package characteristics determine the actual distribution of the on-chip temperature. Figure 1, taken from an actual chip, shows the temperature profile across the channel layer (corresponding to the current carrying channel layer of the active devices) on the die, including the cooling effect due to the bond wires conducting heat from the substrate to the package. As can be seen, a global derating factor is inadequate and inaccurate, because temperature varies between cells and wire segments.

If the temperature distribution across a die is not known, overly pessimistic guard bands must be applied, leading to costly and unnecessary design margins. Also, an analysis based on constant temperature cannot detect the design violations that arise from the non-uniform temperature distribution.

Impact of temperature on electrical characteristics

The effects of temperature on other on-chip parameters can be seen easily by looking at leakage power. Technology scaling and design trends in power reduction have caused sub-threshold leakage current to increase exponentially. This continuing trend may cause leakage power to become a dominant source of chip power.¹