Large, rapidly changing currents in a circuit block when multiple gates are switched simultaneously can cause large inductive voltage changes in a low resistance power grid. These voltage changes propagate across the chip with very little attenuation causing timing errors, increased stress in thin gate oxides and, in extreme cases, complete circuit failure.

This article provides designers with an overview of the techniques needed to analyze resistive, inductive and capacitive effects in an array of parallel transmission lines. These techniques can be used to optimize grid dimensions, decoupling capacitance and the placement of vulnerable circuit blocks at the floor planning stage of the design before detailed layout.

Transmission lines

Figure 1 shows part of a typical IC power grid. Alternating power/ground pairs form an array of transmission lines. Lines of the same type on different layers are tied together with vias at crossover points.

In a well-spaced grid the contribution of the complex magnetic flux density at crossover points to overall inductance is small. For the same reason, the coupling between non neighboring wires is also small enough to ignore. A field solver may be needed to accurately characterize inductance in a grid with wide, closely spaced wires. With these assumptions, the grid can be modeled using an array of independent transmission line pairs.

Figure 1 -- An array of transmission lines.

Figure 2 shows a single transmission line pair. All transistors and capacitors connected to each line pair are modeled by distributed current sources and decoupling capacitance.

Figure 2 -- Section of a power grid showing current sources and decoupling capacitance.

Figure 3 -- Short section of a transmission line.

Figure 3 shows a short section of the transmission line pair. Voltage changes across this section of wire are given by:

Equation 1

where dx is the length of the section, w is the wire width, R_s is the sheet resistance, and L is the inductance per unit length of the wire. The difference between current entering and leaving the section is

Equation 2

where I_o is the current per unit length flowing from Vdd to Gnd across the section and C is capacitance per unit length. Voltage changes in the ground wire are equal in magnitude and opposite in sign to changes across Vdd (both have equal resistance/inductance and current changes of equal magnitude in opposite directions).

Figure 4 -- Equal and opposite voltage changes in a power grid

At low frequency, the time dependent terms in equations (1) and (2) are small and IR drop (and static ground bounce) dominate the grid voltage change. At high frequency in a low resistance grid the time dependent terms are dominant. When all current sources I_o attached to a low resistance grid are switched off equations (1) and (2) reduce to the following (differentiate (1) with respect to x and (2) with respect to t):

Equation 3

This has wave like solutions:

Equation 4

Substituting (4) in (3) gives:

Equation 5

where v (=wavelength*frequency) is the wave propagation velocity (power noise has a short wavelength in ICs with large decoupling capacitance). A grid with significant resistance also continues to oscillate after all circuits blocks have been switched off. In this case the wave amplitude reduces as the noise travels across the chip.

At frequencies where resistive and inductive voltage changes are both significant, resistance can act to reduce the voltage change in a particular direction. For example, at a falling current edge the two terms in equation (1) act in opposite directions. At a rising edge the two terms are in the same direction. This means that voltage drop is greater than the voltage increase during the cycle. This can be useful if the main aim is to prevent gate oxide stressing. Reducing wire resistance in a power net is not always a good idea.

Power grids

In a power grid all transmission line pairs and crossover points have to be analyzed simultaneously. The analysis is still based on equations (1) and (2). Different colors can be used to plot the total voltage change at each point in the grid.

Figure 5 -- Power grid noise plots

It often improves the clarity of the plot to color fill the space between each wire as shown on the right in Figure 5. The voltage change shown on this plot is the total voltage change between power and ground wires at each point on the grid (figure 4). For example, a voltage change of +100mV at a particular location on the grid means that Vdd has increased by 50mV and Gnd has decreased by 50mV in the region around this point. Similarly a voltage change of --150mV at a particular location on the grid means that Vdd has decreased by 75mV and Gnd has increased by 75mV in the region around this point.

Figure 6 shows the effect of a large number of gates switching simultaneously in a 0.4x0.5mm circuit block (all other circuits are switched off). During the transient, current climbs to 200mA in the first 50ps then ramps down during the following 50ps. This causes a maximum voltage increase in the grid of 55mV and a maximum voltage drop of 90mV.

The total chip decoupling capacitance is approximately 1.7nF distributed uniformly across the chip area, except for the block located below the active gates. This has 200pF distributed uniformly across the 0.4x1.0mm block area. A simple calculation shows that each transmission line pair in this block has 400pF/cm of capacitance, giving a wave velocity of 5.6x108 cm/s and a wavelength of 1.1mm at 5GHz.

A similar calculation gives 2.5mm for the wavelength in the region outside this block. Note the reflections from the ideal voltage source at the chip boundary, the continuing oscillations in the grid after switching off, and the decay in amplitude as the noise travels across the chip.

Figure 6 -- RLCsim simulation of simultaneous gate switching in a circuit block in a 4x4mm IC. Grid wire width 10um, Vdd to Vdd space 80um, sheet resistance 20mOhm/sq, wire inductance 8nH/cm.

The effect of a non-ideal voltage source can be approximated by adding circuit blocks with a finite capacitance around the chip edges (figure 7). In this case not all of the noise energy is reflected back into the chip. A proportion of the noise travels through the external supply. This suggests that on-chip and chip to chip signaling through the power supply may be possible if the signal can be efficiently extracted from all the other supply noise. Decoupling blocks might be used to protect on-chip circuits by directing most of the signal to the external supply or specific regions on the chip, and resistance can be used to dissipate energy where required.

Figure 7 -- Approximating a non-ideal voltage source

Conclusion

The design of high speed integrated circuits requires careful power planning to avoid circuit failures, speed variations and timing problems. This article has shown that techniques based on transmission line theory can be used at the pre-layout stage to analyze power noise related problems in IC design. The method can be used during floor planning to select appropriate power grid dimensions, decoupling capacitance and to place sensitive blocks in 'quiet' regions of the chip. The same technique can be used to investigate possible new types of signaling which make use of existing wiring on and off chip.

Donald Bennett is a device physicist. He was formerly with ST Microelectronics in the UK, and has research interests in TCAD, including wave propagation in conductors. Now he markets the the pre-layout power planning tool RLCsim.