The demands on companies creating analog, custom digital, RF and mixed-signal designs have grown exponentially in the last decade. Economics and competition are forcing custom design teams to move to advanced process technologies and integrate the functionality of previously independent ICs onto a single silicon die. In fact, many teams are forced to skip process nodes to integrate with massive digital logic at 0.18 or 0.13 microns, or even nanometer scale technologies.

These market forces are colliding with the technical realities of having to design exponentially more complex designs with exponentially more physical effects. Advanced mixed-signal designs can have over 100K analog transistors and over 100M digital transistors (including memory). Moreover, they face an astounding and ever growing number of physical effects in their packaging, power grid, interconnect, devices and substrate — any one of which can cause an expensive re-spin, if not kill the project. All of this makes it much more difficult than ever to create designs that meet all of their specifications and their schedule — in other words, to deliver silicon that is right on time.

Dealing with today's complexity and physical effects requires an advanced custom design methodology that combines the speed of top-down design with the silicon accuracy of bottom-up approaches. Most advanced design teams are already moving to this pragmatic "meet-in-the-middle" approach. However, their efficiency and effectiveness in doing so is fundamentally limited by inadequate design environments.

This paper describes the triple-threat facing advanced custom design teams: economics, complexity, and physical effects. It then describes traditional design methodologies and the problems that design teams face using today's design tools to adopt a meet-in-the-middle approach. The paper next outlines an advanced custom design methodology that combines top-down speed with bottom-up silicon accuracy. Perhaps most importantly, the paper concludes with the requirements for a next-generation custom design platform to support this approach.

Custom design teams are creating designs phenomenally more complex than just a few years ago. Looking ahead, the design challenges will be increasingly difficult. Leading design teams will undoubtedly adopt meet-in-the-middle design methodologies. They will be easy to identify. They will be the ones that deliver silicon that is right on time.

2 LEADING CHALLENGES IN IC DESIGN

The primary drivers in custom IC design are economics, complexity, and physical effects. As depicted in Figure 1, while economics tends to drive design towards more integration and smaller geometries, the cost of dealing with the exponential growth of design complexity and demanding physics tends to resist a smooth move forward.

Figure 1 -- Key drivers of economics, complexity, and physics

It is important to note that no matter what process node a design team is currently using, the complexity and physical effects curves are exponential in both directions. This means their current designs are much more difficult than previous generations and that next-generation designs will be all the more challenging.

The growing economic demands require ever more insight into a team's ability to deliver silicon that meets all of its specification and is delivered on schedule — silicon that is right on time. Given increasing complexity, design teams need a faster design platform to meet schedule. Similarly, given increasing physical effects, they also need a more silicon-accurate design platform to ensure that the design is meets all of its specifications.

2.1 Economic cost drivers in custom design
As design teams strive to keep pace with their customers' demands of "more for less," they are encountering a vast number of new costs that once represented only a fraction of the cost of the final product. For example, in 1993 a typical printed circuit board (PCB) contained tens, if not hundreds, of discrete components. In today's designs, many of those discrete components are integrated onto a single semiconductor die.

By pushing significant amounts of analog, mixed-signal, RF, and large digital content into a single chip, the systems customer can reduce the level of design effort required to produce a finished product. This capability is not without drawbacks as higher frequencies, larger pin counts, and smaller geometry processes have also increased costs for manufacturing and packaging. For example, a typical 1993 mask set for a 0.5m design cost about $30,000. The cost for a mask set for a 0.13m design has risen to around $600,000.

Ten years ago most designs could be placed in standard packages for less than a dollar. Today's complex, flip-chip packages are custom designed, and the package design alone can cost as much as $175,000 per iteration. Design teams must carefully balance the tradeoff between the cost of increased integration and the increased cost of delivering such a solution.

2.2 Increasing design complexity
The demand of "more for less" is also increasing the complexity of new designs. A state-of-the-art design in 1993 typically consisted of a dozen analog blocks of modest performance for an overall analog transistor count of less than 10,000 devices.

Today's state-of-the-art AMS designs often contain an order of magnitude more analog transistors in 30 to 40 blocks, with operating frequencies pushing 10GHz and dynamic ranges of 70db or more. Integration of large amounts of digital into these designs pushes the transistor count past 200-250 million. Obviously, designs of this size can no longer be managed through the same manual techniques used in the past.

Figure 2 -- Increasing complexity requires a fast methodology

Another aspect of today's designs is the introduction of "operating modes." While a semiconductor that performed a single function was perfectly acceptable 10 years ago, today's designs are often called upon to perform radically different operations depending on system configuration. For example, a cell phone design in 1993 only had to contend with operation in a single, analog cellular system (such as AMPS). TDMA began to appear within the next couple of years, and suddenly cell phones had to manage the shift between analog and digital signals.

Today's cell phones are required to work in Europe (GSM), Japan, North America, and Asia (CDMA with different standards for each region). Topping it off is the rise of band switching in which the entire RF front-end circuitry must contend with multiple carriers within bands, and multiple bands (such as 1.75 GHz or 1.9 GHz). This means that testing the central chip of the phone is essentially equivalent to testing an entirely different design for each new operating mode.

The rise of portable products and multiple operating modes means that designers are turning to multiple power supplies of dramatically lower voltage and power dissipation which radically complicates the test and debug picture.

Design complexity is also being driven by the rise of AMS intellectual property (IP) providers, which are delivering complete blocks to their customers for integration. While the use of third-party IP reduces the amount of design that a team must develop, it also raises the complexity of the integration, test and verification phases.

2.3 Increasing physical effects
As geometries shrink and frequencies rise, physical effects play an increasingly dominant role. In 1993 design teams could abstract away most of the physical effects and rely on simple models for most sections of the design. By 0.13m, there are a growing number of effects (RC parasitics, IR drop, inductance, electromigration, high-frequency effects and substrate noise) that demand silicon-accurate models and specialized analysis to ensure working silicon.

Ten years ago the majority of silicon re-spins were due to simple problems such as wiring errors. Today's design tools have eliminated most of these simple errors, but as a result, the problems encountered now are far more insidious than in the past. For instance, up to 80 percent of the problems in a state-of-the-art design are the result of a failure to account for some unanticipated physical effect that was not modeled or due to some unanticipated interaction between blocks or modes, such as digital noise in sensitive analog circuitry.

Figure 3 -- Increasing physical effects requires silicon-accurate methodology

Many of these insidious effects come together, resulting in first silicon fraught with problems. Traditional debug methods may no longer apply. That means that the design must be created correctly, with as many of the physical effects modeled as accurately as possible, before the design goes to fabrication.

When the design methodology fails to model the silicon accurately, the design team often has no choice but to spin the silicon. Consider the integration of analog and RF with large digital content. The analog and RF circuitry has traditionally existed on its own chip, making it much easier to isolate noise in the system and prevent coupling into the sensitive nodes of the circuit. When these sorts of design components are integrated onto a single die, the problem cannot be ignored. Without some form of very accurate silicon-substrate modeling, the problem might not even be known until silicon comes back from the fab.

The RF and analog are typically designed by separate teams with disparate tools, leading to difficulties during final chip integration. High levels of integration are driving the need for silicon-accurate substrate models. In particular, integrating noise-sensitive analog and RF with large amounts of "noisy digital" requires accurate substrate models. Besides noise coupling, the substrate is also sensitive to a variety of thermal effects that must be considered.

Devices in today's designs are also becoming more sensitive to a variety of new physical effects which require new models, such as multi-threshold voltage operation, intra-die variation, and device aging (reliability modeling). The need for this extra silicon accuracy is driving the use of complex models and placing additional performance demands on the overall methodology.

Smaller geometries are driving new interconnect issues like dishing, erosion, wire distortion, and electromigration. Higher frequencies are also exposing new requirements for interconnect models.

The power distribution grid suffers a new host of problems not seen in 1993. Today's designs are suffering the traditional problems of electromigration, IR drop, and localized hot-spots caused by excess current density.

Higher complexity is pushing IC package design. As designs get more complex, the I/O density increases to cause new problems in package parasitics — especially at high frequencies. Simultaneously, power density is on the rise and causing new thermal effects that can have catastrophic impact on design reliability.

2.4 Market share loss
The largest single cost to a semiconductor company is a cost that a finance department does not see until the company is in financial straits. There is no account payable for the loss of market share when a competitor gets to the socket first.

Failure to deliver a semiconductor on time may cause systems companies to look elsewhere for the component. Tightly coupled to this is the opportunity cost of having your design team working on a design that will not take significant market share, when they should have been working on the next-generation component.

The central problem in market share loss is late delivery. As the turnaround time for a silicon spin grows from a few weeks to a few months, adding a single unplanned spin can be financially disastrous.

Figure 4 -- The economics of optimizing total value

Figure 4 shows the relationship between a market opportunity and the speed and silicon accuracy of the design methodology. As shown in the top curve, the probability of successful silicon is zero until the initial design is complete, after which the probability increases based on the design team's ability to verify the design and fix any problems.

If a design team goes to tapeout too early, they are likely to have to re-spin silicon, resulting in lost market opportunity for that chip, as shown on the bottom diagram. Too many silicon spins, and the market window is closed. Note that the bottom diagram reflects the market impact for that IC only. The opportunity cost is actually much greater because all subsequent projects are delayed.

Faster design methodologies shift the development curve to the left and increase the slope of the probability curve after the initial design is complete. Increasing silicon accuracy shifts the curve up and closes the gap between what the design platform reports about the design and what results in silicon.

3 PROBLEMS WITH TODAY'S METHODOLOGIES

Current custom methodologies are largely limited by legacy design environments that were never intended to handle the complexity or physical effects in today's designs.

3.1 Traditional methodology overview
Design teams traditionally practiced bottom-up methodologies in which designers created low-level cells, circuits, and blocks and aggregated the results together as they went-eventually integrating the entire chip. While this approach ensures silicon-accurate information throughout, it is far too slow for complex ICs. Moreover, design teams have no real insight into system-level functionality or problems until far too late in the design cycle.

For these reasons, there has been a move to top-down methodologies that begin with complete behavioral models of the IC or system. These models are very fast, enabling early high-level verification. The design team decomposes these models into progressively smaller blocks as they walk down the design hierarchy, eventually reaching silicon-accurate circuit design.

The problem with this approach is that silicon-accurate information appears too late in the process, often resulting in catching major issues late in the schedule. Additionally, this methodology does not adequately support legacy designs or IP.

Advanced custom design clearly needs a combined top-down, bottom-up approach that is both fast and silicon-accurate. The meet-in-the-middle methodology provides the only pragmatic way to deal with increasing complexity and increasing physical effects.

3.2 Tool advances and issues
Most design teams today already use a meet-in-the-middle methodology. However, design tool limitations severely restrict the overall efficiency. There are significant shortcomings in each of the major tool areas: simulation, layout, and silicon analysis.

3.2.1 Simulation
Improvements to the bottom-up approach include the rapid rise of fast simulation. Augmenting the use of traditional Spice engines, design teams have deployed fast Spice simulators to reduce the time required to simulate large blocks of transistors for analog, mixed-signal, and large digital designs. Although effective, the fast Spice algorithms often sacrifice far too much accuracy, and the design team must expend inordinate effort to correlate the results of multiple simulators to each other and the silicon.

Alternatively, the top-down approach has turned to AMS behavioral simulators to provide a significant reduction in the time required to develop the top-level model and prove the architecture of the design prior to detailed implementation. However, the effort required to develop the top-down silicon-accurate models has delayed the deployment of this approach in many companies.

Increasing the integration of RF components also requires simulators that augment traditional Spice. Since RF designs tend to be very difficult to analyze in the time domain, designers have turned to alternate analyses including periodic steady state and harmonic balance. While these techniques can provide very fast simulations for RF components, integrating this IP into a time domain simulation presents a number of problems that must be addressed. Design teams are often faced with correlating the analysis of RF components in the frequency domain with those of the simulations in the time domain.

In today's designs, it is not uncommon to see the need for all four of the traditional simulation engines to come into play on the design to address the analog, mixed-signal, RF, and digital components.

Design teams still find themselves struggling to align different simulators with different model equations and syntax and simulation results. Another major time loss is the need to replicate and synchronize the top-level system specifications across different tools.

3.2.2 Layout
Layout tools have gone beyond simple polygon-level layout and have added concepts like connectivity and automatic design-rule checking. While these improvements have increased designer productivity, they have also led to reduced tool performance. Extra effort is required to create or repair parametric cells and manage the ever increasing number of design constraints.

Smaller geometries, growth in complexity, design rules, and constraints all contribute to a deluge of information — too much to be managed manually. To address the increasing number of constraints, the design team requires a mechanism that can manage constraints from a central location and distribute them to different tools.

Design teams also need early estimation based on top-level routing between blocks and fast layout or estimation within blocks to manage the integration of the full chip. Teams working with multiple design domains must address the different floorplanning requirements when mixing digital, analog, mixed-signal, and RF components in a single design, and they must be able to consider the chip in its entirety.

New tools for automated layout synthesis in analog circuits have helped provide rapid block estimates and initial layouts. Since analog layout tends to be very complex, these tools have not always provided the layout engineer with the full set of features required to rely on this approach.

Another requirement is the ability to mix and match the traditional layout engineer's approach to sophisticated layout synthesis systems. Existing IP developed prior to the introduction of automation usually lacks the constraints to drive a synthesis system. The layout system must provide the ability to manage both with a minimum of extra effort. Layout tools must be as fast as possible to address the increasing demands placed on them by today's designs.

3.2.3 Silicon analysis
One key area that is seeing many tool improvements is silicon analysis. New problems brought on by smaller design geometries and higher frequencies require that design teams address a variety of physical and manufacturing effects much earlier than before.

In designs 10 years ago, a design team could work with simple, static models of both interconnect and substrate. In today's designs, where geometries approach 0.13m, effects like wire edge enlargement (WEE) change the widths of closely spaced wires, and subsequently change the result used to calibrate the tools. The WEE effect means that a single, static measurement of coupling capacitance and wire resistance is no longer sufficient to achieve silicon accuracy.

Another outcome of smaller geometries is the need to address manufacturing effects like dishing and erosion. Due to differences in hardness between silicon dioxide and copper, the chemical and mechanical polishing (CMP) process dishes out the top of the interconnect and erodes areas of low density wiring. To compensate, the design team must add metal fill to compensate for the dishing and erosion, which changes the overall capacitance of the chip. These changes must be reflected back into simulation to ensure that the design will still operate after metal filling.

Higher frequencies are also causing new problems in substrate noise coupling and the need for induction extraction. Inductance modeling is becoming mandatory for designs above one to two GHz. Although inductance extraction is relatively easy, finding the current return path (through the substrate, interconnect, or other path) has pushed the problem closer to a full-chip problem rather than an isolated, block-local analysis.

The size and complexity of today's circuits has a significant impact on power distribution grids, which are now much longer and more subject to IR drop. Analyzing for IR drop is increasingly important as chip supply voltages decrease. If not accounted for in the design process, the on-chip IR drop and loss through the package can reduce operating headroom to the point where it is very difficult to get the circuit to function. IR drop in signal lines can lead to signal degradation and affect circuit function and performance.

Perhaps the most insidious of all effects is that of electromigration (EM), which is increasing due to greater current density in smaller wires and because of the effects of high-frequency signals, called "skin effect," which tends to concentrate the current on the surface of the wires. EM is particularly dangerous because it generally cannot be caught during tapeout and it is not obvious on first silicon that the problem exists. EM can take weeks or months to manifest, leading to massive field failures after months of customer use.

3.3 Integration challenges
Design teams have recognized that reuse of existing IP is one way to address the time pressures of today's designs. However, as they face higher levels of integration they have to come to grips with the challenges related to integrating complex IP into new designs — on time and within specification.

3.3.1 Challenges related to analog, RF, and mixed-signal IP
One way of getting designs done faster is through the integration of existing analog, RF, and mixed-signal IP. While this approach has a positive impact on the design chain, there is often a heavy cost as many more considerations come into play.

When components resided in their own packages, much care could be taken by the original design team to insure that each component operated as advertised. Shifting standalone components to same-die IP causes an increased demand for silicon accuracy as these components are integrated.

Figure 5 -- Reuse is becoming critical in mixed-signal designs

Many design teams have responded to the need for a silicon-accurate methodology by running critical AMS blocks on test chips. The AMS test chip provides many benefits, such as silicon proofing of designs and correlation back to the simulation results. Although the use of test chips has provided higher silicon accuracy for unknown blocks, it has the down side in the delay it introduces as the test chip moves through the fab.

3.3.2 Meshing different design and test methodologies
Each unique design domain has its own methods and techniques for the development and testing of IP. The methods used to design analog differ radically from the methods for digital, and even RF design.

The problem is aggravated when these sections of the design are integrated. Because digital design is almost always done in the time domain, and because RF is almost always done in the frequency domain (for simulation speed), integrating these two design styles on the chip can mean that the simulation time of the entire chip is exasperatingly long.

The same is true for the test and verification phases of the design flow. The tests used for digital are not the same as those used for analog. And again, the analog is not the same as the RF portion of the design.

A new methodology for addressing today's designs must go beyond parallel yet unconnected design flows by providing a full-up integration of all tools operating across the domains, and providing the fast, scalable analysis with a solid base in silicon accuracy.

3.3.3 Design collateral and IP sharing
Each unique piece of semiconductor IP is accompanied by a large amount of design collateral in the form numerous associated files, test setup documents, results, and documentation not typically managed by existing design systems. This collateral carries its own demands for completeness and correctness and represents a significant investment from the design team.

Design collateral data is often at the heart of flow problems. One tool may produce data that the next tool in the flow cannot reuse, leading to lost time when the design team must duplicate or recast the collateral into a format usable by the next tool.

As an example, a design constraint intended to tell a layout tool that two transistors must be matched is often specified in the schematic capture system. This matching constraint now needs to propagate down the tool flow to every tool and designer that is concerned with matched devices. Unless the various tools understand the constraint, and understand the format that the constraint is specified in, the flow is likely to break. Design collateral also affects the ability to share and reuse IP across designs and design teams and between companies.

4 AN ADVANCED CUSTOM DESIGN METHODOLOGY

This section outlines an advanced custom design (ACD) methodology for mixed-signal designs that contain a mix of analog, custom digital, RF, or digital cell-based circuitry. These types of designs require a fast, silicon-accurate design methodology.

In the ACD methodology, the top-level model of the design serves as a target, the design work progresses towards completion, and the bottom-up design work adds additional detail. Thus, the top-down design and the bottom-up design work will eventually meet in the middle. The speed and accuracy with which these two models can be driven together determines the effectiveness of the design platform.

This methodology makes continuous design evolution possible. It has the ability to manage both the design data from multiple design domains and the associated design collateral, all while eliminating the tedious manual efforts traditionally required during such integrations.

4.1 Key concepts
The ACD methodology is based on several core concepts including silicon accuracy, managing design collateral, fast top-down design, silicon-accurate bottom-up design, mixed-level continuous design evolution, and a meet-in-the-middle approach.

4.1.1 Silicon accuracy
Silicon accuracy is the ability to predict that what you see in the design environment is what you will see in silicon. Achieving predictability requires the calibration of simulation and circuit models used in the design process to ensure that design teams have the correct information for success.

Inaccuracies in known or expected effects are compounded in new advanced processes where it is not uncommon to see variations of three to five percent on a weekly basis. For the majority of a design, this presents no problem. For sensitive components of the design, the team has two choices. The first is to design around the variability of the process (for example, using complex compensation circuitry). The second choice is to update the design continually as the process drifts.

The new methodology allows the design team to focus their efforts on the core of the design while accommodating the correlation of known silicon effects. This allows for better modeling and calibration of expected effects and for proactive management of the effects of process changes over time.

4.1.2 Managing design collateral
The ability to consider chip integration from the very beginning of the design and drive the design forward under the auspices of the overall specification is critical to the new methodology.

As shown in section 3.3.3, each block of the design is accompanied by significant amounts of design collateral. The methodology must consider the design of the blocks and the design collateral used to support the final integration. The methodology must accommodate the collateral as provided, and not require the team to perform extra work to support integration.

4.1.3 Fast top-down design
The methodology makes extensive use of a fast top-down approach in both simulation and physical design with multiple abstraction levels at the system and behavioral levels. The top-level simulation and physical models both start with abstractions and estimations which are further refined as the team proceeds. In both cases, the models are available at all times and serve as a guide as the design is evolved and updated.

For example, a preliminary route can be created with early estimations of block sizes and aspect ratios, and followed by a top-level extraction. This information is then used as block specifications early on, saving time in block design.

Simulation and physical design tasks are set up and performed early and are leveraged continuously throughout the rest of the design process for verification, routing, extraction, and other steps. The design team finds and fixes issues early, not during tapeout.

4.1.4 Silicon accuracy from bottom-up design
A silicon-accurate methodology utilizes the bottom-up approach extensively to verify at the transistor level, and ensures that the design meets specifications. Detailed parasitic information is used to a designer's discretion to achieve the accuracy level necessary based on the design specifications versus the process capability.

The bottom-up approach provides silicon accuracy by moving measurements of the silicon into detailed models, and building those calibrated models into blocks and finally into the chip. In the physical design area, the ability to bring in full layout data to perform accurate silicon and analysis provides confidence that the design will meet performance criteria.

The bottom-up design process also supports an abstraction capability, with silicon-accurate calibration into faster models that can be run in larger simulations, the results of which can feed the top-down design stream. The designer is able to determine how accurate a calibrated model needs to be at the next integration level, ensuring that the accuracy of further simulations can be guaranteed.

4.1.5 Mixed-level and continuous design evolution
Combining the top-down and bottom-up approaches gives the design team the freedom to mix and match as needed to achieve a fast, silicon-accurate design. This mixed-level capability leads to a fast, reliable, and predictable design process by continuously controlling the design under test in the context of the larger system. Continuous design evolution relies on the top-down and bottom-up design styles being simultaneously executed and combines both the detailed simulation and the physical design plan. This gives the design team the ability to monitor and flag issues whenever the design data changes.

The mixed-level approach also supports a fast design process by feeding new top-level design requirements to the block level in real time and identifying new top-level requirements due to block-level design realities.

4.1.6 The meet-in-the-middle approach
The custom methodology takes a meet-in-the-middle approach as the most pragmatic method to achieving predictability on complex designs. The methodology leverages the fast capabilities of top-down design together with the silicon accuracy capabilities of bottom-up design. When merged, the majority of the design activity cannot be described either as top-down or bottom-up but a combination of the two.

Figure 6 -- The meet-in-the-middle approach

As shown in Figure 6, multiple abstraction levels are used to represent the evolution of each piece of the design. In simulation, behavioral models are used initially, which grow more detailed as the design process moves forward, bringing in measurements and data ultimately from post-layout analysis.

In physical design, initial size estimates and initial block abstracts are updated as more design information becomes available, driving toward the final, actual layout at the top level. The designer is actually working in the middle most of the time, with some blocks at the fast, top-down stage, and some annotated with additional design data and silicon accuracy information using the bottom-up process.

Abstraction levels serve as the foundation of the meet-in-the-middle approach. The simulation abstractions range from purely behavioral at the top to silicon-accurate, calibrated models towards the end of the process. The physical abstractions range from early estimations to final route and extractions. The methodology has a complete set of predefined abstraction levels which are continuously updated through the design process and support the mixed-level capability.

Driving the meet-in-the-middle approach requires an initial translation of the chip's requirements into the specification and leverages the use of system-level models, testbenches, and measurements. The testbenches may be derived from specific IC specifications (such as 802.11a) and ultimately feed the specification-driven environment. The specification-driven environment then drives the chip-level and block-level tests in a manner consistent with the original requirements of the design.

4.2 Advanced custom design methodology
The advanced custom methodology is targeted at design teams working on full-custom designs comprised of components from each of the major design domains of analog, custom digital, RF, and digital standard cell.

These designs require a fast, silicon-accurate design methodology that is always predictable to achieve the highest likelihood of early success. Design engineers must be allowed to focus on their areas of expertise. Since the chip integration task is so complicated and critical, it needs to be considered from the very beginning and then continuously through the entire design process. The design process must be able to support first-time designs and design derivatives seamlessly.

In the methodology, the top-level model of the design serves as a target, the design work progresses towards completion, and the bottom-up design work adds additional detail. Thus, the top-down design and the bottom-up design work will eventually meet in the middle. The speed and accuracy with which these two models can be driven together determines the effectiveness of the design platform.

The advanced custom methodology is designed to make quick work of integration. A key aspect of the methodology is the ability to manage the design data from multiple design domains and the associated design collateral, all while eliminating the tedious manual efforts that have been traditionally required during such integrations.

4.2.1 Silicon accuracy in the advanced custom methodology
In Figure 7, each box in the diagram can be considered a block of the chip, where both block and block I/O requirements exist. Viewed from the full-chip level, the end simulation system must support full mixed-signal capability from both custom and digital points of view.

Figure 7 -- The advanced custom design methodology integrates multiple flows

Each design domain needs the ability to produce this collateral as natural fallout of the design process. Each block's design collateral (netlists, models, simulation setups) must also be 100 percent compatible for the integration to run smoothly. Should any designer have to perform extra work to support integration, it becomes unlikely that integration will occur on time or within budget.

4.2.2 Systematic increases in silicon accuracy
Key to the advanced methodology is never forgetting anything previously learned. As the design progresses, systematic increases in silicon accuracy must be rapidly encoded and put to immediate use.

This ability shows itself across all aspects of the design process. At the lowest levels of the design, continuous updates in the fabrication process must be rapidly accounted for as it affects the devices and all objects built up from them. The accuracy of sensitive blocks can be explored and that knowledge applied to derivative blocks and larger components in the design. These increases in accuracy require a mechanism for propagating any changes rapidly through the design.

4.2.3 Process design kits and device models from silicon
Process design kits (PDKs) feed technology and process data to the design process and must be verified to support an advanced design methodology. Best addressed prior to the design start, the PDK must be fully analyzed and verified by the design group to ensure it can support the design process. Risk areas must be identified at this point, before final chip integration steps are performed.

The end deliverable of this process is a silicon-accurate PDK that supports each step of the design process. Design engineers should have guidelines as to the design margins necessary to achieve success and avoid excessive over design. PDKs may also require updates during the design phase. This requirement may be enforced on the team as the process technology changes, or as better models are created to solve other problems.

4.2.4 Capturing the design process with the design
The advanced custom methodology must address the issues surrounding the design, use, and reuse of IP in new designs. As discussed, a major portion of this process involves the creation and management of design collateral which documents not only the IP, but the testbenches and supporting design information required to use the IP. Collectively, this requirement means that the design process must be captured along with the design itself.

Unless this information is captured, future reuse of the design is limited (whether as IP in a larger design or as the basis for a derivative design), because the design team faces serious time issues as they struggle to either recreate the information or suffer the problems induced without the benefit of having it available.

4.2.5 Application of automation to the design
Much of the design team's effort is subject to automation, assuming that the steps automated have been captured and can be replayed. This is important because engineering change orders (ECOs) can happen at any time in the design process and may require rework, which requires re-verification. The ability to remember, modify, and replay key steps of the process on demand provides significant time leverage to the design team.

4.2.6 Continuous design verification
With the physics of the silicon captured in the PDK, and a mechanism for capturing the design process, the design team now has the capability to verify the design continuously. This ability keeps the design team on top of problems and gives them the needed visibility to make corrections early. It also prevents those problems from rippling throughout the design.

For example, if a problem is found in a critical block after integration and first chip assembly, the design team may have the entire design to contend with. If the problem is found the first time the problem block is integrated with its neighbors, the problem can be fixed without fear that a change might cause re-verification of the rest of the design.

5 CUSTOM DESIGN PLATFORM REQUIREMENTS

The advanced custom design (ACD) methodology described in the previous section requires a new-generation custom design platform that enables efficient meet-in-the-middle design across multiple design domains.

5.1 Speed and silicon accuracy
In order to address the issues of economics, complexity, and physics, the custom platform must deliver silicon accuracy at the highest possible performance. The silicon accuracy provided must have a solid base in silicon measurement and must accommodate the physics of the implementation process. The performance of the platform must always be as fast as possible with the ability to trade off speed for accuracy at the discretion of the design team.

Figure 8 -- Custom design platform enables fast, silicon-accurate design

5.1.1 Advanced silicon modeling
Silicon accuracy is predicated on the ability to rely on simulation results within a predictable design margin and have silicon results validate the approach. As such, advanced silicon modeling needs to be part of the platform, with the underlying simulators tied closely to the device modeling technology to ensure the most accurate simulation results. Device modeling capability is also needed as the design teams make custom additions to PDKs and ensure model consistency across those additions.

There are three aspects to advanced silicon modeling. The first is the ability to deliver continuously updated silicon-accurate information and to quickly identify and respond to changes when needed.

The second aspect is the ability to have all tools, where applicable, use the same equations when performing computations on the silicon-accurate data. This capability ensures that the design team can stay focused on the design rather than the design tools, or their interpretation of the silicon data and their calibration back to the silicon.

The third aspect is the ability to remember what has been learned and put that knowledge into action when needed. Given this ability, the custom platform must allow designers to capture the complete solution (including testbenches and measurements) and use it across all parts of the flow.

5.1.2 Specification-driven design environment
All designs proceed according to the specification of the design. In the past, designers held the specification in their heads or in their notebooks. The custom platform must deliver a specification-driven environment that encodes the specification along with the design so that continuous verification can quickly alert the design team to pending problems before they commit to silicon.

To manage the large volumes of design collateral and accommodate the need for capturing the design process with the design, a specification-driven design environment is required. This allows for easy setup of continuous regressions, supporting the characterization of silicon accuracy and the fast, optimized execution of the simulation strategy.

5.1.3 Multi-mode simulation
The methodology requires a comprehensive simulation capability that must simultaneously extend through multiple design domains (analog, RF, custom digital, digital standard cell) and support the mixed-level capability and the meet-in-the-middle approach. The custom design platform must deliver an advanced simulation capability that accurately represents every part of the design from the silicon process to the top-level behavioral model of the system.

Key to this capability is the presence of silicon-accurate information across the design flow. From the behavioral models to HDL to the major transistor-level blocks to the highest accuracy circuit simulation, all tools must have access to the latest silicon accuracy information. The simulation engines must also eliminate any discrepancies between results by utilizing common syntax, models, and equations wherever possible.

Simulation must extend deep to support silicon accuracy at the lowest abstraction levels, as well as enable high-level descriptions for fast execution.

5.1.4 Accelerated layout
Driven by the increase in design sizes, the custom platform must deliver mechanisms for accelerated layout. The primary requirement is that the layout tools must be as fast as possible in all aspects. Given the massive sizes of today's designs, the layout system must be as fast as possible in order to keep the system interactive.

Another key requirement is top-down floorplanning, which helps the team quickly identify and repair problems in block placement and the subsequent interconnect. As the design gets more complex, concepts like constraint-driven, connectivity-driven, and design rule-aware layout become mandatory. This capability allows multiple designers to encode and respect design constraints, ensure correct connectivity, and prevent design rule errors automatically.

Automation is another key requirement. Designers must be given the tools that automate everything from single wire routes to device automation to floorplanning. Additionally, the custom platform must provide layout synthesis for large, complex cells that normally require hundreds of hours of manual effort.

5.1.5 Detailed silicon analysis
As the design nears completion, the level of silicon analysis required at the full-chip level increases. The custom platform must provide capabilities for detailed silicon-accurate analysis of power and signal integrity, electromigration (EM), IR drop and substrate noise in analog and mixed-signal designs. Also included in the analyses is the ability to diagnose and manage manufacturing problems like dishing and erosion.

These analyzes rely on silicon-accurate data from the PDK and simulation results to highlight potential problems, often not covered through traditional simulation. Predictability can only be achieved through a parasitic-aware methodology supporting continuous evolution of the full design through a fast, silicon-accurate process.

5.1.6 Full-chip integration and mixed-signal chip finishing
At some point, all of the design blocks must come together with all aspects of the final chip. The custom platform must provide the capability to bring in huge design components, provide floorplanning and top-level routing, and perform final analyses on the entire chip.

The platform must support the ability to integrate massive physical sections of the design and provide a basis for launching fast, silicon-accurate silicon analyzes at any point in the process.

The chip integration capability allows the design team to bring in successively complete sections of the design from all of the design domains. This capability also supports associated design collateral, smoothing the integration wherever possible.

5.1.7 Universal data hub
Seamless integration of design data across multiple design domains is a central theme to the ACD methodology. As such, a universal data hub is needed to allow for data to move across design tasks, and from completely different design processes. For example, digital standard cell design is not directly covered within the ACD methodology; however, design data coming from the digital standard cell design process must enter the platform easily to achieve a fast design process and maintain silicon-accurate information. Execution time and capacity are also key components to the data hub, as large databases often need to be manipulated at various times through the design process.

The universal data hub must extend through the front-end and back-end tool infrastructure, especially in tasks like IR drop, EM, substrate noise analyzes, and RC extraction, which all require a detailed melding of the front-end and back-end data. The universal data hub also addresses the need to share IP between other design projects and between IP providers.

With a unified database underneath all of the individual tools, those tools can natively share design data while getting the speed benefits of a modern database architecture.

6 CONCLUSION

The need for a new methodology to address the ever increasing demands of today's designs has driven the need for a new design platform. As design teams struggle with the triple threat of economics, complexity and physics, the custom platform delivers a fast, silicon-accurate basis for developing designs.

Ted Vucurevich serves as a Cadence Senior Vice President. He is responsible for driving advanced technology development and directing Cadence Laboratories. In his prior role as chief architect at Cadence, Vucurevich helped develop the strategies and technology initiatives in system-on-a-chip-(SoC) based design, DSM infrastructure, software interoperability, design methodology development, and Internet-based electronic system design.

Lavi Lev serves as a Cadence Executive Vice President, with responsibilities as General Manager of the Products & Solutions Business. Prior to Cadence, Lev was Senior Vice President of Engineering at MIPS Technologies. He has also led engineering teams at Silicon Graphics, MicroUnity Systems, Sun Microsystems, Intel Corporation, and National Semiconductor.