Part II : Pre-RTL and RTL Exploration Tools

In order to test drive the tools in this series, I contacted Virtual Silicon, Inc. who kindly provided me with 0.13 micron and 0.18 micron standard cell, datapath and memory libraries. My sincere thanks for their help in making this series possible.

For the Verilog intellectual property (IP) employed as the data for this series, I contacted OpenCores to use their OR1200 RISC processor core and support logic. I also used the VGA/LCD Controller core developed by Richard Herveille and Rudolf Usselmann of ASICS. The sources for these cores are freely available at the OpenCores web site.

I employed a dedicated testing and evaluation network in my home office for running the EDA tools and writing this article series. Based primarily on 850Mhz PIII desktop PCs running Red Hat Linux 7.2, there were also Sun Ultra workstations running Solaris 2.7, and 850Mhz PIII laptops running Windows 98SE and NT.

In this installment I'll be demonstrating detailed pre-RTL design flows using the SOCarchitect tool from Icinergy Software and the DesignArena tool from InTime Software. Then I'll demonstrate detailed RTL exploration design flows with the TeraForm tool from Tera Systems, Inc. and the DesignWarrior tool from InTime Software. My sincere thanks to these companies for making evaluation copies of their products available to me in order to write this series.

Pre-RTL Exploration Tools

I outlined a generalized pre-RTL design flow in the first installment of this article in Figure 5, and I will now examine the details of this flow using two very different tools -- SOCarchitect and DesignArena.

These tools both function in the pre-RTL design domain, but approach the problem from completely different directions. The DesignArena tool from InTime Software is intended mainly to be used with pre-packaged IP, and is largely automatic in operation. The SOCarchitect tool from Icinergy Software can also be used with prepacked IP, but can be used for IP creation as well, and is intended to capture "design intent" as a design is incrementally refined.

DesignArena

DesignArena is a client-server based tool that can be deployed on a web page for library and IP vendors, and is designed so that it can keep the details of a technology and IP library confidential and concealed from the end-user. The user interacts with a Java based client to select and configure IP blocks, define I/O pins and estimate die area. The tool can produce a preliminary floorplan and data sheets.

Figure 7 - DesignArena Flow

The following figure shows a screen capture of the DesignArena estimates for the vga_lcd design.
Figure 8 - DesignArena Results Page

The following figure shows a screen capture of the DesignArena data sheet display.
Figure 9 - DesignArena DataSheet Output

SOCarchitect

SOCarchitect straddles the pre-RTL, RTL, and gate-level design domains and can be used in a variety of flows. Since I am discussing pre-RTL flows I'll start with the tool here, but it can also be used at many other points in the design flow, as it has interfaces for importing and exporting RTL, LEF/DEF, GDSII, and several other formats. The SOCarchitect tool can be used to coordinate and document a design as it is incrementally refined throughout its lifecycle.

Figure 10 - SOCarchitect Flow

The above flow is only a representative one, and many others are possible with this tool. SOCarchitect includes a TCL command interface, and the functionality of the tool can be expanded by the user to perform more complex operations.

The following figures show screen captures of the SOCarchitect tool at various points in the design flow. In Figure 11, I use the LEF import feature to import a library to calibrate gate sizes.
Figure 11 - SOCarchitect Importing LEF

In Figure 12, once the RTL is read in, I can optimize my floorplan and begin to analyze congestion and timing impacts.
Figure 12 - SOCarchitect Optimize Floorplan

Figure 13 demonstrates a routing density view in the top frame, and a timing violation view in the bottom frame. If any of the interconnects had violated my timing budget, they would have turned from green to red in the display.
Figure 13 - SOCarchitect Timing Violations

Figure 14 is an example PDF Data Sheet generated by the SOCarchitect tool for the vga_lcd evaluation design.
Figure 14 - SOCarchitect Generated PDF Data Sheet

RTL Exploration Tools

I outlined a generalized RTL exploration design flow in Figure 6 and I will now examine the details of this flow using two different virtual silicon prototyping tools, namely TeraForm and DesignWarrior.

TeraForm

Tera Systems, Inc. has been doing well with their TeraForm and TeraForm2 tools at companies like LSI Logic, NEC and Fujitsu. The TeraForm tool can automatically convert RTL code into a TeraGate based silicon virtual prototype, a high level abstraction of the RTL functionality. Similar to a "synthetic library" the TeraGate representation models logic, layout, and timing at the RTL level, achieving very fast turnaround times as designers change and refine their RTL code.

A vendor standard cell library from, say, IBM, Fujitsu, or Virtual Silicon must first be processed into a high level TeraGate library before it can be used by the TeraForm tool. The TeraGate library generation is accomplished at Tera Systems, Inc. using a nine-corner modeling process to build high-level functions like multibit adders, subtractors, and multiplexors. The TeraForm tool then partitions and maps your RTL code onto these precharacterized library functions. Each function has slow, medium, and fast implementations to allow the tool to perform area and speed tradeoffs.

Figure 15 below depicts a typical design flow using the TeraForm tool. The user starts by reading in the RTL code, then elaborating, partitioning, estimating and laying it out at the register-transfer level. Once the RTL floorplan and layout are complete, detailed static timing analysis is available that accurately models interconnect delay based on the expected floorplan.

Figure 15 - TeraForm Flow

Like most current generation EDA tools, TeraForm incorporates a TCL language interpreter that can be used to expand the capabilities of the tool and implement customized user procedures. These can be used to customize the design flow, or the interface scripts can be used to drive other tools, such as physical synthesis tools.

Special thanks go to Dirk Seynhaeve of Tera Systems, Inc. for providing a copy of TeraForm2 on short notice in order to generate the following screen shots and help me complete this article on time.

As you can see from Figure 16 below, the left hand panel displays both the logical and physical hierarchy of the RTL, with the RTL source in the left hand panel, and the TCL command window at the lower left.
Figure 16 - TeraForm - Reading the RTL Sources

In Figure 17 below, we perform a search for all high level adder instances in the design, which identifies them in both the logical hierarchy and the physical hierarchy.
Figure 17 - TeraForm - Finding All Adder Instances

Figure 18 below depicts the automatically generated RTL floorplan.
Figure 18 - TeraForm - Performing the RTL Layout

Figure 19 below demonstrates some of the tracing power available in the TeraForm tool. We select a slow path of interest in the timing view within center right hand panel, which simultaneously highlights the path (in red) in the TeraGate schematic representation in the lower right panel. It also highlights the path (in red) in the RTL layout in the center panel, while the path in the RTL source is highlighted (in red) on left hand panel.
Figure 19 - TeraForm - Tracing a Slow RTL Path

Once you have identified the cause of the slow path, you can make changes to the RTL and rerun the flow within minutes. It's a much faster method to achieve high quality RTL code and design timing closure.

DesignWarrior

The DesignWarrior product from InTime Software is an integrated RTL design environment that performs automated RTL floorplanning, timing, and analysis. It is a fully hierarchical system, and provides links to drive physical synthesis and layout tools, in either flat or hierarchical modes of operation.

DesignWarrior uses a "synthetic library" of high level functions that is created from a vendor standard cell library using the InTime Technology Wizard tool. This tool automatically invokes synthesis and timing analysis to build the required design kit database. Once the design kit database is built, the user invokes the InTime Project Wizard to define the parameters, environment, team members, and their design responsibilities.

Once the project is well defined, the user can enter the Integrated Design Environment (IDE), and begin to import and analyze their RTL code. Figure 20 below outlines the overall flow.

Figure 20 - DesignWarrior Flow

The Project Wizard introduces the concept of "published objects" that allow design teams to control the integration of complex SOC designs in managable phases. The Project Wizard creates the Project Environment File, and initializes the Project Database structures. The Project Wizard design flow is illustrated in Figure 21 below.

Figure 21 - Project Wizard Flow

The Project Wizard has detailed library performance analysis capabilities that give the user fine-grained control over technology targeting. This is particularly important for achieving high performance designs, and reducing the number of synthesis iterations to achieve timing closure when moving from the RTL domain to gate-level domain. I have made several screen captures that illustrate to power of the Project Wizard to perform detailed library performance analysis. Figure 22 depicts the performance of all the NAND gates in the design kit, and Figure 23 depicts the performance of the flip-flops in the design kit.
Figure 22 - Project Wizard - NAND Gate Family
Figure 23 - Project Wizard - Flip-Flop Gate Family

You will notice in the above figures that it is possible to change both the gate loading and input slew rate and recalculate these graphs.

The following figures show the detailed analysis for a NAND2 gate from the specified design kit (UMC 0.13 micron).
Figure 24 - Project Wizard - NAND2 Best Case
Figure 25 - Project Wizard - NAND2 Worst Case

Figure 26 demonstrates one of the uses for this type of detailed analysis, marking selected gates as "Don't Use" in the project database. The project database stores detailed information about the project environment, along with parameters such as maximum fanout, maximum loading, and preferred routing layers. These can be used when DesignWarrior drives downstream synthesis and layout tools from within comprehensive "auto-piloted" design flows.
Figure 26 - Project Wizard - Don't Use Gate Marking

Also, the user could quickly compare several different libraries and determine if the desired project goals could be met in a 0.18 technology or a 0.13 technology.
Figure 27 - Project Wizard - Logic Depth Analysis

Once the design team is satisfied with the project goals, requirements, and the technology selections they can then invoke the DesignWarrior IDE and begin to import their RTL source code. Figure 28 depicts a representative design flow using the IDE.

Figure 28 - DesignWarrior IDE Flow

There can be many variations on the above typical flow, as there are a number of paths in and out of the DesignWarrior IDE. The IDE has the capability to drive downstream third party synthesis and layout tools in either flat or hierarchical modes of operation. The TCL command interpreter allows the user to extend the functionality of the DesignWarrior IDE and implement customized user procedures. Figure 29 shows a screen shot of the DesignWarrior Import RTL operation.
Figure 29 - DW IDE - Import RTL Source

In the above screen shot you'll notice the small icon/tool bar at the top of the display, which follows the basic flow: Import RTL, bind RTL, create synthesis hierarchy, create physical hierarchy, and create floorplan/layout.
Figure 30 - DW IDE - Create Synthesis Hierarchy

Above in Figure 30, you'll see the screen shot for the Create Synthesis Hierarchy operation, which performs the partitioning of the RTL design prior to running synthesis.

Conclusions

I've demonstrated several design flows using virtual silicon prototyping tools. The basic premise of these virtual silicon prototyping tools is to increase the quality of the RTL code prior to gate level synthesis by modeling physical effects at a higher level of abstraction. By working at a higher level of abstraction these tools are usually processing about one-tenth the number of instances, with runtimes that are an order of magnitude faster than gate level synthesis. By modeling physical effects earlier in the design process, we can reduce the number of synthesis and layout iterations and achieve rapid timing closure.

Coming next in Part III

Coming next in Part III of this series, I'll demonstrate how to integrate these flows with common physical synthesis tools to yield gate level netlists and initial floorplans for place and route tools.

Tom Moxon is the founder of Moxon Design, an electronics design consulting organization. He has designed integrated circuits for a number of client companies, including Cray Research, Adobe Systems, Hewlett Packard, Silicon Graphics, Rohm, and Hyundai Electronics. Tom has been working for several years on web enabling EDA and CAD infrastructures, and is researching EDA applications using XML/XSLT, RDF, DAML, and XML-RPC. When he's not "slinging gates" for a living, Tom is often called upon to torture test new EDA tools before they are inflicted on the remainder of the engineering community.