In this interview Becker Sze, senior design manager at Averlogic, tells why his company chose Incentia over Synopsys synthesis tools. Sze likes DesignCraft's fast run times and cost advantages, but he acknowledges that there are still a few missing capabilities.

EEdesign: How large are your chips, and what are the challenges?

Sze: The smallest one is 50K logic gates and 72K SRAM; the largest is 500K logic gates and 500K SRAM. Right now, because of the processes we are using, the most challenging thing is the speed. Because of the extensive NRE cost, we are staying at 0.35 or 0.25 microns. Foundries are TSMC and UMC. But we also want to make the chips as fast as possible, from 166 MHz to 200 MHz, so we spend a lot of time fine-tuning the timing around synthesis and rewriting synthesis scripts.

We generate netlists and send them to a service company to do place and route for us. It's a Taiwanese company called Innochip.

EEdesign: Which tapeouts have you done with Incentia's DesignCraft?

Sze: We've done four. I think the biggest was 250K gates with several blocks of SRAM, but I wasn't responsible for that one. The previous chip that I taped out with Incentia wasn't a big one - it had 70K gates plus 1 Mbit SRAM in 0.25 micron technology. But we're designing one now that has a half-million gates of random logic with several blocks of SRAM. We're doing placement and routing now.

EEdesign: Were you using Synopsys Design Compiler before, and why did you move to Incentia?

Sze: We have Synopsys only for VHDL, and two years ago, we started to migrate from VHDL to Verilog. For Verilog design today we totally use Incentia. For VHDL we also use Incentia, but if we need to cross-check something, we run Synopsys to double-check the results.

In the beginning when Incentia came to visit our company, we weren't interested at all. We had never heard of Incentia, and Synopsys dominates this market. But they said Via [Via Technologies, Taiwan] was using their timer and evaluating their synthesis tool. We have connections with Via chip designers, and we checked with them. They said they'd bought the tool, and they provided a very good reference.

At that time we did a comparison with one of our old designs, written in VHDL. To be honest, the result was about the same, both in timing and area. In timing-driven compilation, the Incentia result is equal to or slightly better than Design Compiler. However, Incentia is much faster.

EEdesign: How much faster?

Sze: In our test cases, we found it only spent about 70 percent of the CPU time of Synopsys' Design Compiler. I think that saves at least a few weeks to one month, because we usually need to run synthesis quite a few times. Before, when we used Synopsys, whole-chip synthesis would take at least a day. When we switched to Incentia we had faster turnaround times, and we can try this, try that, and try more combinations.

EEdesign: How's the capacity of DesignCraft, in terms of handling large blocks?

Sze: Both Synopsys and Incentia handle our designs pretty well. The biggest block, so far, is about a half-million gates. But Incentia did core dump a few times, and the tool showed a brief message, "internal error, please contact Incentia." They fixed it very quickly, probably the next day.

EEdesign: Are there a lot of iterations between synthesis, and placement and routing?

Sze: We do experience quite a few iterations between synthesis and place and route. I don't think that's because of the synthesis tool. In my experience it's because the wire-load models the library provides were not that accurate. Or, they're too aggressive. For example, we used Artisan's library, and we found they would omit a physical layout value. So that's why a lot of iterations occurred.

EEdesign: Have you tried Incentia's DesignCraft Pro physical synthesis tool?

Sze: It's still in beta test stage. I've tried it on one of our current designs - not a tapeout yet - and it really helped a lot. It reduced the critical path delay from 9.5 ns to 7 ns.

If we use physical synthesis, we can provide a detailed placement before we send the netlist to layout. However, it still has its limitations because it's just an estimation. The tool only does placement, not the actual layout. It can estimate the wire load and calculate the delay, but the number is not a real number - the real number still has to be extracted from the layout tool. So, there is still some difference.

EEdesign: Does Incentia offer all the capabilities Synopsys offers?

Sze: Almost everything. They have VHDL, Verilog, a timer, and a DesignWare type library. With Synopsys you have to buy separate licenses. With Incentia, it's all bundled. The price is affordable, and that's one important reason we chose Incentia.

EEdesign: Are there any missing capabilities, compared to Design Compiler?

Sze: We found there is one function Incentia doesn't have, and it's very important. When you're doing timing optimization, and there are several clock domains, and one domain cannot meet timing, Synopsys can still optimize all the other clock domains. But Incentia can't do that. If one clock domain fails, all the clock domains are reduced to the same number.

EEdesign: Is Incentia's library of arithmetic functions comparable to Synopsys' DesignWare?

Sze: Yes, according to their manual, they have that kind of capability. I didn't test them all, but in my application, when I needed a multiplier, it did provide that function.

EEdesign: Synopsys offers power synthesis. Does Incentia do anything with power?

Sze: No, as far as I know, Incentia doesn't provide any power calculation or estimation.

EEdesign: What about test?

Sze: Incentia offers test synthesis with scan chain insertion, but I haven't tried it, so I have no comment.

EEdesign: Is the Incentia synthesis tool easy to learn?

Sze: Yes, and that's a very important feature. It's very, very similar to Design Compiler. A user with Synopsys experience can very easily learn how to use the Incentia tool. 60 or 70 percent of the commands are exactly the same, although some are slightly different. For instance, Synopsys uses "compile," and Incentia uses "optimize." Incentia also provides a tool that can convert Synopsys script files to Incentia script files.

EEdesign: How's the support from Incentia?

Sze: The support is very good. The support engineers are very experienced, and they're located here in San Jose.