    |
|
||||||||||||||||
|
Exploring new design flows -- RTL synthesis |
||||||||||||||||
|
Tom Moxon
(03/07/2002 3:00 PM EST) URL: http://www.eetimes.com/showArticle.jhtml?articleID=16504568 |
||||||||||||||||
|
Editor's Note: In Part 2 of this series,
consultant and ASIC designer Tom Moxon
covered several trends in virtual silicon prototying design flows.
In this installment of the series he'll show how to link these flows with several different RTL synthesis design flows.
Part 3: RTL Synthesis
In the previous section we concentrated on improving the quality
of the RTL code using virtual silicon prototying tools.
After RTL floorplanning, these tools can help drive RTL synthesis by providing partitioning data, placement data,
custom wireload models and control/run scripts.
There have been a lot of improvements in RTL synthesis tools
over the past few years, with a number of new tools available to designers,
as well as some existing tools that have now matured enough to become useful.
For Verilog source and RTL synthesis scripts, I've been using several of the following designs available on the web:
These are representative packed IP blocks, and they come with example synthesis scripts, constraints,
and design files. In the OpenCore conventions, the "design_name/syn" directory would be used
for RTL synthesis with Design Compiler.
However, in order to avoid temporary file and naming collisions, I tend to use separate
subdirectories for different vendor/tool views, with the "design_name/syn" directory as the
RTL synthesis reference directory, containing the master constraint files.
When simultaineously using multiple tools, this facilitates separation of the different vendor/tool views.
I often use the company symbol in the subdirectory naming scheme,
so I'll typically have :
The basic strategy used on these RTL synthesis examples
for exploratory, first time synthesis is a
classic overconstraining leaf module bottom-up compile.
A default set of constraints, wireloads, and scripts are used for
these first initial builds to provide base results.
As the virtual silicon prototyping process progresses,
these constraints, wireloads, and scripts are optimized
as the design is refined at different levels of detail.
As development of the leaf modules stabilizes,
this is followed by a full chip top-down compile
and final chip level optimization/assembly.
 Figure 29
Several of the RTL exploration and floorplanning tools can automatically partition your RTL code into blocks that are efficiently sized for RTL synthesis. Here is an example of this synthesis heirarchy generation capability with automated heirarchical synthesis script generation. I'll go into this in more detail later in Part 5, when I present several different automation techniques.
Design Compiler
Synopsys has the lions share of the synthesis market, with Design Compiler and Physical Compiler available in most ASIC design houses. The Synopsys-Avanti "powerflow" is already familiar to most ASIC designers, so I'll refer you to the ESNUG archives and the DeepChip website, by John Cooley, for more information about Synopsys synthesis issues and techniques.
 Figure 30
DesignCraft
Incentia Design Systems has been making good strides in the ASIC synthesis market, with tapeouts from several customers.
DesignCraft is Incentia's logic synthesis product. It takes an RTL design and synthesizes a gate-level netlist. TimeCraft is Incentia's full-chip, gate-level, static timing analyzer product. DesignCraft Pro is the physical synthesis solution in Incentia's product family. It links logic synthesis with Incentia's proprietary placement technologies, and it performs simultaneous logic and physical optimization from RTL descriptions to placed gates.
Designers familiar with the Synopsys Design Compiler (DC) have no problems quickly adapting to DesignCraft. I had good results using the Incentia TransCraft script translator to import DC-shell scripts. I was also able to use the TCL interface to "replace" commands with my own versions for compatibility with existing scripts.
Figure 31
The DesignCraft GUI is integrated with the embedded TCL interpreter, yielding an easy to expand user interface. I've been able to run several of the evaluation designs and have been impressed with the quick results. Below are example screenshots including the read and schematic views.
DesignCraft - Read View Screenshot
DesignCraft - Schematic View Screenshot
Topomo
Get2Chip is also finding their place in new synthesis flows with their Volare and Topomo products, intended as architectural and system compilers for SOC designs, respectively.
Volare reads a "pins-out" cycle-accurate functional description of a design and creates a timing accurate gate-level netlist. Many commercial behavioral synthesis tools will only take into account the delays of the behavioral elements (datapath blocks and logic gates) but will not account for the delays associated with FSM blocks, multiplexers, or wiring loads. That can make it difficult to correlate the timing behavior of the generated RTL code with the gate-level netlist generated after RTL synthesis.
Volare works in conjunction with Topomo, a system compiler for SOC designs, to perform silicon virtual prototyping. Volare is driven by the design goals to select a micro-architecture based on the target technology library. Topomo then performs topology modeling, partitioning, placement, shaping, synthesis, and wire planning, yielding placed gate level netlists.
A great feature of the Get2Chip products is the end user licensing agreements. Get2Chip site licenses allow customers to put Volare/Topomo on their Intranets integrated with other Web-based tools. This kind of flexibility is greatly appreciated by customers.
I'm looking forward to working with these tools in more detail, and I'll have more to report after running some of the sample designs through them.
Figure 32
Volare screen shot
Synplify ASIC
Synplicity has done well in the FPGA synthesis market, steadily building market share. Building on the speed and capacity of their FPGA synthesis tools, Synplicity has also entered the ASIC synthesis market.
Many designers like the ability to perform rapid system prototyping using FPGAs prior to committing an ASIC to silicon. The Synplicity Certify tool can perform drag-and-drop paritioning across several physical FPGA devices. The Synplicity Amplify physical compiler for FPGAs lets you sqeeze the performance from each partition. Then you can use the Synplfy ASIC synthesizer to generate your ASIC netlists from the same RTL sources.
Synplify Pro has been pretty easy to use for FPGAs, and the Synplify ASIC synthesizer looks as easy to use. I'm looking forward to running some of the evaluation designs through their latest release, as I just received new license files.
Figure 33
New Design Flows
I've shown several of the new choices available for the RTL synthesis step of the design flow, moving from RTL level to a gate level netlist representation. Most designers are now following this step with heirarchical gate level placement and analysis/optimization tools such as First Encounter, TeraPlace, or Physical Studio prior to detailed routing. We'll examine some of these flows in Part 4 of this series.
Figure 34
Designers now have some variety in performace, capacity, platforms, licensing agreements, and support plans from several synthesis vendors. Flexible licensing is also an issue for companies with many locations and intranets. Customers are increasingly demanding Linux platform support, as 1.6 GHz PC's are inexpensive and available. And most people see a fairly linear decrease in RTL synthesis runtimes as the processor speed increases.
Coming next in Part 4
Coming next in Part 4 of this series I'll demonstrate how to integrate these flows with physical layout and signal integrity tools.
Tom Moxon
is the founder of
Moxon Design,
an electronics design consulting organization.
He has designed integrated circuits for a number of
client companies, including Cray Research,
Adobe Systems, Hewlett Packard, Silicon Graphics,
Rohm, and Hyundai Electronics.
Tom has been working for several years on web enabling
EDA and CAD infrastructures, and is researching EDA
applications using XML/XSLT, RDF, DAML, and XML-RPC.
When he's not "slinging gates" for a living, Tom is
often called upon to torture test new EDA tools
before they are inflicted on the remainder of the
engineering community.
|
||||||||||||||||
|
All materials on this site Copyright © 2009 TechInsights, a Division of United Business Media LLC. All rights reserved. Privacy Statement | Your California Privacy Rights | Terms of Service | About |
||||||||||||||||
