Deep submicron design is no longer just about timing closure - designers must also cope with signal-integrity and power challenges. At 0.18 microns and below, considerations such as crosstalk, IR drop, power dissipation, and electromigration begin to take center stage - but tools and methodologies are in scarce supply today. The following contributed articles, from both vendors and users, will help you find some solutions to signal-integrity and power challenges.
- Signal integrity permeates design process. Cadence Design Systems' Jim McCanny shows how you can manage signal integrity from early design planning through post-layout analysis.
- Crosstalk, power haunt UDSM designs. Avanti's Bari Biswas offers a tutorial on crosstalk noise, power dissipation, power net voltage drop, and signal and power net electromigration.
- IC layout must avoid crosstalk problems. Tak Young of Monterey Design Systems discusses techniques for global routing, crosstalk avoidance, and noise propagation cell models.
- Deep submicron design is more than just 'noise.' Going beyond crosstalk, Celestry's Dale Pollek and Lifeng Wu look at IR drop, electromigration, hot carrier injection, and negative biased temperature instability.
- Static crosstalk analysis assures silicon success. Synopsys' Bijan Kiani and Texas Instruments' Anthony Hill provide a tutorial on static crosstalk analysis, and show how it's used at TI.
- Early power estimates guide IP selection. Chip designer Stephen Voegelin explains how his company, Aura Communications, selects IP blocks for low-power applications.
- Signal integrity drives post-layout verification. Grego Sanguinetti from telecom provider Accelerant Networks shows how his company designed a high-speed, mixed-signal network backplane product.
- ALF facilitates SI-aware design flow. Authors from multiple companies team up under the Accellera banner to show how the Advanced Library Format (ALF) handles power and signal integrity.
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