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Interconnect noise models plenty noisy |
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Raminderpal Singh
(06/04/2002 3:30 PM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=17407853 |
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 Looking at today's system-on-chip world, it is easy to concern ourselves with how designers accurately model interconnect noise (glitch and delay) between intellectual-property blocks. Take a 1-GHz digital signal along a single six-line bus between a microprocessor and a random logic block. How is one going to model mutual inductance effects as one of the bit-line switches in the opposite direction of the others? Capturing new-age effects such as mutual inductance and substrate coupling can be complex for a chip integrator to come to grips with. So, do we need new interconnect models or do we need better formats, for representing the information?
The direction for this discussion will vary as technologies scale to sub-0.1 micron. Today, Advanced Library Format (ALF) 2.0 has appeared as a strong contender as the format of choice. It claims to handle many types of "signal integrity: to model crosstalk, noise, electromigration, hot-electron effects, interconnect, electrical models for delay, crosstalk and reliability calculations" above ALF 1.0. It is also an IEEE standard.
On the other hand, the Standard Parasitic Exchange Format (SPEF) primarily handles interconnect parasitics and is also part of an IEEE standard. And then there's the Standard Interconnect Performance Parameters (SIPPs), which focuses on interfacing process data between industry extraction tools-an important problem for SoC designers.
Let us not forget that the application for the models will dictate its requirements. An interconnect in the core of the microprocessor may have different requirements from that of one between DRAM and control logic blocks. The former may be implemented on low-level metal layers (M1 or M2) with signal frequencies at 1 GHz+, and the latter may be at higher-level metals with sub-200-MHz signal frequencies. Mutual inductance, for example, can depend on the circuit structure and the signal frequencies (and the signals themselves, for that matter) on the interconnects, as well as being complex to extract accurately and efficiently.
Where do we go from here? How do we close on what we need, and when, from the designer's point of view? Well, the VSI Alliance is just beginning to develop its 2.0 standards document. The requirement for a suitable model or format is one of the first topics under discussion, including analysis, for example, of ALF 2.0 vs. the model shown in the figure above. From there, we need to get EDA buy-in and finally designers need to be prepared to adopt the solution. This will no doubt be a long and nonlinear discovery process. The good news is that those same designers and EDA developers are the ones doing the analysis at VSIA.
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Such standards have the advantage of being relatively easy to support in EDA tools, but such formats are generally limited to first-order effects in the 0.13- to 0.18-micron space. As a counterpoint, a newly developed empirical model should be able to capture all of the signal integrity issues, either as a collared black box or possibly as a gray box. The accompanying figure shows a common parasitic model for coupled line structures. This common transmission model shows how the various parasitics of the metal and silicon substrate can be included. The negative is that the model needs to be compatible enough that EDA vendors will be able to use it or migrate to using it-a very difficult but real issue, as we all know.