The IEEE-sponsored ISPD conference, which draws participants from industry and academia, has become a premier showcase for research in IC physical design. This years conference opens with a keynote speech by Raul Camposano, CTO of Synopsys Inc., who will overview physical design challenges from floorplanning through manufacturing.

New to ISPD this year is a session on benchmarking, which will feature two papers on partitioning and placement algorithms. Igor Markov, assistant professor of electrical engineering and computer science, will offer a paper on "benchmarking for large-scale placement and beyond."

"In this talk, I am going to review motivations for benchmarking, especially for commercial EDA, analyze available circuit layout benchmarks, and point out major pitfalls in benchmarking," Markov told EE Times. "We argue that customers of EDA tools and even EDA vendors will greatly benefit from open benchmarking."

The other benchmarking paper, which looks at the "optimality, scalability, and stability" of placement algorithms, is co-authored by Jason Cong, co-director of the VLSI CAD lab at the University of California at Los Angeles. This paper follows Cong's controversial ASP-DAC paper, in which he argued that current placement algorithms leave so much wire length on the table that chip designs are effectively several technology generations behind.

In other sessions, IC placement will be the topic of papers offered by IBM, Cadence Design Systems, Intel, Synopsys, and the University of California at Santa Barbara. Magma Design Automation will present a paper outlining a methodology for power grid design, while Motorola will describe its approach to signal integrity management.