Technical papers from IBM Research detailed the first practical use of a statistical timing analyzer at the 40th DAC here last week. And at a special session called "Coping with variability: the end of deterministic design," both IBM and Intel Corp. listed probabilistic tools as a priority area into which they will plow R&D dollars to tackle sub-90-nanometer design. Such is not the case for commercial tool vendors like Synopsys, Cadence or Magma.

EDA vendors are just beginning to look at probabilistic methods, so-called because they relax the metrics of various parameters in order to obtain the best results for different design goals. "Probabilistic tools aren't yet on our product schedules," said Louis Scheffer, a Fellow at Cadence Design Systems Inc. "There are several methods being pondered in academia, and most of it is really raw."

"The EDA industry's lack of knowing what silicon vendors really need, unfortunately, isn't a big surprise," said Gary Smith, chief EDA analyst at Gartner Dataquest, who predicted nevertheless that vendors of commercial design automation tools eventually will catch on.

Academics and researchers say that mature probabilistic technology will allow users to home in as early as the register-transfer level (RTL) on the right mix of yield, timing and power by using a mix of statistical algorithms. Proponents believe that statistical methods will enter every aspect of design and drive the next retooling, from RTL down through manufacturing (see box, page 90).

"I think this is the start, but it is still very early in a sea change from deterministic tools to probabilistic tools," said Chandu Visweswariah of IBM's Thomas J. Watson Research Center, who is considered a leading researcher in probabilistic tools. Visweswariah said the technology will become necessary at 65- and 45-nm nodes.

"Variability is here; make it your friend," he quipped.

His IBM colleagues Kerim Kalafala, a software developer, and Srinath Naidu, a doctoral student at Eindhoven University of Technology in the Netherlands, demonstrated the statistical timing analyzer technology. After implementing three statistical timing algorithms, the researchers came up with a timing-vs.-performance curve in 15 minutes, tested with Monte Carlo simulation. Performing that same feat using IBM's respected EinsTimer static tool took 68 hours, also tested with Monte Carlo simulation, the researchers said. The team said the technology will start off as an extension to EinsTimer but could grow to replace it.

But to really take off, say scientists who are watching this area closely, probabilistic technology requires intimate correlation to silicon. For that reason, some believe this design methodology may give the edge to vertical ASIC vendors, which develop their own design tools closely correlated to their silicon. This breed of chip maker may well obtain the edge needed to dominate the 65-nm and lower manufacturing nodes-and perhaps even the 90-nm node-killing the momentum of suppliers that rely on a flow from customer-owned tooling to the foundry, observers said.

"We think the super IDMs [integrated device manufacturers] like IBM and Intel are pulling away and will stay one or two generations ahead of the COT-to-foundry guys," said Dataquest's Smith. "Statistical timing analysis and other probabilistic methods are a big area where they are doing it."

But Taiwan Semiconductor Manufacturing Co. is on the probabilistic bandwagon too, Ping Yang, vice president of research and development for TSMC, said in response to written inquiries from EE Times. The foundry's managers believe the technology will become dominant in nanometer design, he said, adding that TSMC has in its current offerings and under development statistical analysis tools from multiple third-party vendors and from internal development teams.

A number of academics watching this space, however, said foundries would have to share transistor variation lengths within a chip-chip to chip and run to run-with EDA and library vendors before probabilistic tools could become commercialized. Even the IBM researchers said that data was not easy to get from IBM's own silicon process technology group.

Researchers at IBM and Intel say that they will spend heavily on probabilistic design.

A TSMC spokesman said the foundry "already [supplies its] vendors with this information for both devices and interconnects."

"We believe it is a differentiating strength that we are not betting entirely on one horse, and externally produced tools are developed by competitive vendors who will apply their own core competencies to add additional value," said R&D chief Ping Yang.

Meanwhile, Intel researcher Shekhar Borkar presented a DAC paper on process, voltage and temperature variations and their impact on circuit and microarchitecture. His point was that taking correlations into account is a crucial capability of a statistical timer.

Statistical timing has the potential to improve turnaround time, help manage risk and guarantee first-time-right hardware, he said. And it will have a profound impact on modeling, analysis, verification, synthesis and design methodology, Borkar said.

In his presentation, Visweswariah proposed three novel probabilistic algorithms for statistical timing analysis and parametric yield prediction of digital chips-specifically, microprocessors and ASICs. The algorithms address manufacturing and environmental variations and work in tandem to exploit a needed method as the situation demands.

Visweswariah listed three main reasons why today's deterministic design paradigm is breaking down. Critical dimensions are scaling faster than designers can control them, he said. Second, in recent technology generations interconnect metallization has shown large variability. These new sources of variability are relatively uncorrelated to the earlier ones and are relatively uncorrelated from one metal level to another as well, leading to an explosion in the number of significant and independent sources of variation. Concomitantly, the number of cases, or "corners," of the guard belts required for confident coverage has shot up.

Third, Visweswariah said, across-the-chip line width variation, caused mainly by reticle and proximity effects during lithography and by local density effects, is increasing with each new generation of technology.

Not only must timing verification be performed statistically, Visweswariah said, but so must but other design tasks. "We are presented with an opportunity to reduce the number of sign-off timing runs by applying statistical techniques," he said.

While none of this is particularly new, the number of these effects is increasing and so is their magnitude, he said, rendering worst-casing all of them as simply not practical anymore. Simultaneously, time-to-market pressure is precluding exhaustive timing verification at a ballooning number of combinations of cases and static timer settings.

The solution is statistical static timing analysis, Visweswariah argued, which will simultaneously enable targeting of high-performance chips while providing quantitative risk management.

Implemented and applied correctly, the technique will reduce pessimism, improve verification turnaround time and provide a means for increasing parametric yield, he concluded.

Academics said the design world will inevitably turn to statistical timing analysis, at www.eet.com/story/OEG20030325S0024.

Researchers make a case for probabilistic timing, at www.eedesign.com/news/OEG20021204S0016.