Binachip (San Jose, Calif.), based on research from Northwestern University in Illinois, is hard to categorize. The company's Binachip-FPGA tool will generate RTL code for hardware implementations but is aimed primarily at embedded-software developers who want to accelerate their applications by putting computationally intensive routines into silicon.

"We're not competing with companies that do behavioral synthesis from C to RTL," said Susheel Chandra, Binachip's president and CEO. "We speed up embedded applications." By converting only those portions of software that can truly benefit from hardware acceleration, Chandra said, the technology can provide a 10x to 50x speedup over a pure software implementation.

Binachip's technology is based on software developed under co-founder Prith Banerjee, who today is dean of engineering at the University of Illinois in Chicago. As chairman and chief scientist of Binachip, Chandra said, Banerjee will devote about 20 percent of his time to the startup.

While at Northwestern, Banerjee and his grad students developed the Freedom Compiler, which takes DSP apps written in assembly language and automatically generates RTL Verilog and VHDL code for Xilinx and Altera FPGAs. The compiler was described at the 2004 Design Automation Conference. The technology was patented in 2004, and Binachip holds an exclusive license.

Binachip today has a staff of four--Banerjee, two of his graduate students and Chandra--and is closing a round of venture funding, Chandra said. Given its small size, the company hopes to forge marketing part- nerships with FPGA vendors and embedded-software development companies.

Binachip expects to go into product release in the second quarter with Binachip-FPGA, which selects and converts binary code into RTL Verilog and VHDL. Later in 2006, the company plans to release Binachip-ESW, which will provide tight integration with software development environments.

In 2007 will come Binachip-GPP, which will automatically convert binary applications code from one processor to another--a process that can take months to do manually, according to the company.

One thing that differentiates Binachip from nearly all other electronic system-level (ESL) design companies is its use of binary code, as opposed to C or Matlab. "In an embedded application, you could develop in multiple languages, so just going from C doesn't help you," Chandra said.

There are a number of reasons to start with software binaries, Chandra said. One is language independence. Another is the ability to leverage architecture-independent compiler optimizations. A third is the availability of preexisting binary code for many embedded applications.

But perhaps the biggest reason is that binaries allow "fine-grained" hardware/ software partitioning. The tool, or a user, could pick out just a few lines of code to send off for RTL translation. "Silicon is money," Chandra observed. "You want to transmit just the minimum amount required to meet your performance."

Binachip is proposing a modified design flow in which software is compiled into binary form before hardware/software partitioning. Binachip-FPGA reads the binary code, converts it into an internal representation and maps selected chunks into the hardware. For the remaining code, it reconstructs the binary, with the proper function calls to get data in and out of the hardware.

The RTL Verilog or VHDL code then goes into the normal FPGA design flow. "We do not claim it will be as good as manually generated RTL," Chandra said. "The way I like to look at it is that we will provide a 10x to 50x speedup over the embedded application."

Binachip-FPGA doesn't provide profiling tools; instead, it lets users launch a third-party profiler. It can automatically take profiled data and perform the hardware/software partitioning, but users can also make the selections. Chandra thinks most people will override the automatic process. "These guys know their code pretty well, and they know there's a bottleneck they want to put in hardware," he said.

Binachip supports Xilinx and Altera FPGAs. Processor support includes the ARM7, ARM9, Texas Instruments 6000 DSP series and PowerPC, with Altera Nios and Xilinx Microblaze on the road map. Chandra said partnership discussions are under way with FPGA, EDA and software development tool providers, but nothing is ready for announcement.