In a talk entitled "The benefits of three-dimensional partitioning of printed circuit signal routing," Fjelstad encouraged designers to launch high-speed signals off the top of the package, while routing lower-speed power and ground signals through the bottom, where all signals are routed today. SiliconPipe is a startup company specializing in multi-gigabit interconnect technology.

Fjelstad said that IC packaging and PCB design practices are the limiting factor in chip and system performance today. "The design approach must change," he said. "Silicon, packaging, and PCB interconnects must be considered together in the design process."

Fjelstad said that chip, package and substrate "codesign" is going to be a requirement, and that it must encompass digital and analog circuitry, transient thermal analysis, thermo-mechanical analysis, electrical power distribution, and signal integrity. Other issues include dielectric loss, planarity and warpage, processing temperature, moisture absorption, and electrostatic discharge (ESD).

Performance limitations due to connectors, vias, crosstalk, ESD, attenuation, and skew must be "made to vanish" in order to reach the performance we need, Fjelstad said.

While chips have doubled in transistor count every 18 months, following Moore's Law, pc-board interconnect hasn't kept up, Fjelstad said. "We need to find an improved approach," he said. "Rather than having the processor twiddle its thumbs waiting for the next instruction, let's move interconnect technology ahead so that it has to wait for a signal from the processor."

Stack packaging, in which multiple die are stacked on top of each other, sets the stage for a change in interconnect technology, Fjelstad said. "You have I/O on the package, and die on the upper surface of the package, so why not use that for launching signals off the die as opposed to going down and through?" he asked.

"If you route critical signals off the top of the package in a controlled impedance way, you can get 20 Gbits/second," Fjelstad said. Moreover, he said, this practice results in minimal vias, zero skew, "near zero" chip-to-chip discontinuities, and simpler boards.

"What we're looking at is essentially optical performance with the simplicity of copper," he said. The over-the-top routing creates "elevated super-highways" on the pc-board, he said.

Fjelstad also reviewed other methods of speeding up pc-board performance, including clusters of plated through vias, differential pair connections with reduced stubs, and via placement alternatives that can result in a 30 to 50 percent routing improvement.

There's one hitch with the over-the-top routing, however; the need for better EDA tools. "There are no tools on anyone's desk today that will handle this without a little bit of trepidation," Fjelstad said.

The PCB Design Conference West is located in San Jose, Calif., March 15-18.