About eight years ago, the chip-manufacturing industry began to approach one of those uncompromising physical limits that cannot be ignored: The feature sizes being printed onto wafers by lithographic equipment were about to shrink below the wavelength of the light used to define them. The race was on to find a new approach, with much shorter associated wavelengths, for projecting circuit geometry onto masks. A variety of contenders emerged, featuring new radiation sources. The contenders with the best odds were ion beam, electron beam and X-ray projection.

What won the race? Oddly enough, optical lithography.

Semiconductor fabs have continued to use the same basic optical process up to the current 90-nanometer feature sizes, and no one expects that to change as the industry moves to even smaller features at 65 and 45 nanometers. What happened?

For one, various techniques were used to head off distortions caused by the blurring effect of light wave interference. Phase shift masks employed destructive interference at the boundary between areas to cancel wave-generated distortion. In a process called optical proximity correction (OPC), precalculated geometric elements were added to masks at corners, line ends and other fine details, introducing a predistortion that cancels the distorting effects of wave interference.

And recently, with immersion lithography, water has been introduced between the lens and mask. Leveraging the refractive index of the water to reduce the impact of the wave nature of light should extend current optical techniques down to the 45-nm node, process experts say.

"We went from painting very fat lines with fine brushes to . . . painting small lines with great big brushes. One is easy; the other is very, very hard," said Joseph Sawicki, vice president of the design-to-silicon division of Mentor Graphics Corp.

When feature sizes were much larger than the wavelength of light, there was a direct geometric projection of a mask pattern onto the resist. A rectangular area defining a conducting via would be projected onto the mask as a rectangle. Once a circuit had been designed, a design rule check (DRC) would be run on the generated mask pattern to verify that the pattern conformed to the requirements of a specific fab line. The fab would then guarantee that a predefined percentage of the chips produced by that mask pattern would perform to the limits set by the design--the yield.

"At 250 nanometers, or a quarter-micron, people started doing rule-based OPC: Run a DRC check on the layout. Wherever you see a line end, put a little hammer head on it; every place you see a contact, put bunny ears on each corner," Sawicki said. "At 130 nanometers, contacts disappeared. Line ends got really badly pulled back. At this point, you could not manufacture a chip without OPC."

For chip designers, DRC was accompanied by an indication of where "hot spots"--places where the circuit configuration was likely to produce problems for the lithographic process--occurred in the layout.

Now a trend is emerging in which computational modules that simulate problem areas of the lithography process are being integrated into EDA tools in an effort to make circuit designs more litho-friendly. The systems, fielded by Mentor Graphics, Cadence Design Systems Inc. and Synopsys Inc., bring the traditionally independent spheres of design and fabrication closer together, in a bid to maintain yield as features shrink.

"Nobody really wants to think about lithography during design. There is no one out there in the fabless design community who's itching to know more about lithography," said Mark Miller, vice president of business development for Cadence's design-for-manufacturing group. The thrust of the new tools is to allow designers to continue doing what they have been trained to do--design and lay out circuits. The tools provide DRC, but with an awareness of the more-complex nature of optical imaging at subwavelength dimensions.

"Today, anything to do with litho is all about subwavelength printing. That means frequency-domain analysis or fast Fourier transforms," said Miller. "There is a whole new branch of EDA that is about using computational models to predict where an edge is going to appear based on where you drew it. Now we have to implement a whole new suite of design tools around that contour up in the design flow that will reflect what is actually going to happen in the silicon."

In February, Cadence introduced the Virtuoso RET suite. The resolution enhancement tools, which are integrated with the company's Virtuoso design system, let chip designers run OPC checks while still in the design phase. The tools also simulate how layout structures will print, so the designer can head off as many problems as possible during the design phase. The tool set is not designed to replace the final OPC check, which still needs to be done before sign-off.

Synopsys has integrated resolution enhancement techniques into its design-for-manufacturing products and claims to have the most comprehensive solution for IC design. The company's design suite includes lithography verification as well as mask synthesis and qualification.

"Previously, if you had manufacturing problems, you could prohibit the designer from doing certain things using design rules. You now have rules that encompass whole areas, not just an immediate neighbor. The rules have to be very complex and context-dependent. So we are talking about model-based design correction, not simply rule-based design correction," said Srinivas Raghvendra, senior director for DFM Solutions at Synopsys.

That makes it much harder for the IC designer to decide whether a layout will work simply by looking at it. Many of the aspects of wave interference are counterintuitive, particularly if the designer is simply thinking in terms of basic geometry, Raghvendra said. "When we were young, design rule checks were the golden sign-off. What we are saying now is that you can't have design checks based only on rules; you need models."

Even when all the factors generated by the wave nature of light have been addressed, there is a lower layer of problems that can sink a design. As the device size shrinks, the graininess of the material in which the features are realized begins to introduce errors. The variations in the atomic structure of silicon and associated random changes in the material's electrical characteristics perturb device behavior. And the degree of uniformity in the surface, created within a given tolerance by chemical mechanical polishing, begins to look rougher at smaller size scales.

So even if there were some ideal mask projection system that had no resolution problems, simply shrinking device sizes would introduce errors that the IC designer would have to factor in to the layout process. That level of design verification is being tackled by Stratosphere Solutions Inc., a 2004 startup that has fielded a metrology tool called Stratopro.

"Stratopro will provide data from a variety of topologies--transistor styles and architectures that would be very relevant to the standard designs that would be done on any type of process technology," said Jim Bordelon, co-founder and CTO of Stratosphere. "There may be certain topologies that are not covered well within the litho-modeling framework, and on top of that, there are other types of process steps contributing to yield fallout that the lithography problem isn't going to consider."

Once all the resolution enhancement techniques and litho models have been run, Stratopro will give the fab and chip designer feedback on whether the features are going to produce the correct device behavior. "Our product [takes] a hard look at how well any given lithography model or OPC treatment is actually performing from an electrical standpoint, not just from a pattern fidelity standpoint," Bordelon said.

"If there is an error in the model, any high-level simulation tool is going to give false results," noted Prashant Maniar, the other co-founder of Stratosphere. "If a particular feature is failing in a particular way due to an OPC model, any other place where that feature exists, you are going to see a similar type of failure. . . . Within the die and from die to die and wafer to wafer, those defects are going to multiply. The impact could be quite dramatic, particularly in the early stages of yield ramp."

Stratosphere has been developing physical-modeling systems based on Monte Carlo simulations of the effects of parameter variations in the silicon substrate in an effort to predict how a given feature, assuming it has been correctly defined in the first place, will behave in silicon.

"What we are offering is a tool that enables the whole litho-aware design flow. We believe that it is critical for improving the efficacy of that flow," said Maniar.

The question posed by the various efforts to extend optical lithography is how far they can go. At some point, the increasing stack of tools needed to maintain yield--and costly enhancements to litho tools--will produce diminishing returns on investment. But for the coming 45-nm node, the current litho-friendly design tools, combined with immersion techniques, should fill the bill.

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