To address these design challenges, temperature analysis must be included in the design process. The circuit design process must include a better methodology to understand the heat flow from the die through the package and the heat flow within the die.

Understanding on-die temperatures resulting from heat flow permits a circuit designer to address the sensitivity of the circuitry to temperature variations throughout the design process. A better understanding of the temperature variations in the design provides the circuit designer with insight into where to place temperature sensors and focus design efforts on design challenges such as reliability.

A design flow methodology that provides temperature variations with an understanding of the electro-thermal interaction is required for today’s analog and mixed-signal designs. These design challenges and the methodology to address them are covered in this document.

Heat flow from die to package

Steady-state thermal specifications of ICs are typically provided in datasheets using a point model that includes maximum junction temperature, maximum ambient temperature, maximum allowed power dissipation for a given package, and the thermal resistance (RΘ_JA junction to ambient) of the package. Unfortunately, however, the assumptions in the point model — which is really just an approximate description of actual thermal implications — can lead to errors in the design and implementation of the product.

The point model fails to take real-world physics into account. What really happens is that the flow of heat through silicon and then through the package structure to the ambient environment causes an elevated die temperature, which results in a heat transfer path from the IC to the ambient.

The heat transfer between the IC and the package case (RΘ_JC junction to case) is conductive, through thermal compounds and die attach materials, to the heat sink (R&Theta_CS case to heat sink) and beyond (RΘ_SA heat sink to ambient). To analyze the heat radiation and convection effects on the IC, package software tools model these parameters as equivalent thermal resistors.

Some approximations may be introduced in the equivalent thermal resistor model, especially where heat is radiated from the package case directly to ambient. The rate of heat transfer is a non-linear function of the size of the package and the rate of airflow, but the thermal resistor is considered linear. The distributed powers will usually provide a different volume average junction temperature from that predicted by the point average model.

This non-linear rate of heat transfer produces a different effective package thermal resistance model than the one specified for the product. The point model does not indicate the temperature gradients that it causes; what determines temperature gradients are the package boundary, material, bond wire locations, and position of the power sources.

Temperature contours on the die, including the effect of bond wires, is shown in Figure 1. The point model with its single junction max temperature using package theta and max average power dissipation (which does not consider the distributed power and hence distributed temperature values) leads to discrepancies between the assumed and the real world situation. Consequently the physical implementation of the product can be different from the datasheet specifications.

Heat flow on the die

Power, dissipated by individual devices as heat on the surface of the die, flows from the devices through the silicon substrate, giving rise to temperature gradients along the surface of the die. Heat flowing through the metal interconnects, combined with the power dissipated in interconnects, also causes temperature gradients along and between the metal layers. These temperature gradients can strongly affect circuit performance and reliability.