Designing for low power consumption is a challenge that extends throughout the entire chip industry now, from high-performance MPUs to cell phone chip sets. "It used to be designs were either high performance or low power--not both," said Behrooz Zahiri, a Magma Design Automation Inc. product manager. "But power is not an option anymore." For the EDA vendors, that means power analysis tools need to be aware of timing and area impact, trading off and optimizing one vs. the other.

With leakage now accounting for roughly half of all power consumption at leading-edge process nodes, the focus has shifted to turning off circuits completely when they are not being used. Power gating is now a primary tool in the effort to keep power under control, along with clock gating--which reduces active power but does nothing for leakage--multiple operating voltages and multiple threshold voltages.

Mark Buccini, a manager in the low-power MCU product line at Texas Instruments Inc., said that as technology scales to 90 nanometers and below, leakage rivals active-power dissipation, and customers must do more than employ multiple threshold voltages.

Managing threshold voltage "keeps power under control to a degree, but as we scale it gets worse," Buccini said. "It is a losing battle: You may get lower active power, but leakage and standby are going up. Removing power from nonactive elements is one way of controlling leakage."

C.C. Chai, a design services product manager at Taiwan Semiconductor Manufacturing Co., said TSMC will discuss two major test chips at the Design Automation Conference, planned for July. The chips use voltage islands, back-biasing and multithreshold voltages, or MTCMOS, an acronym that goes beyond threshold voltage to encompass the larger power-gating techniques.

Some designs can turn off large blocks, a coarse-grained approach, while others are better suited to shutting down small circuits, the fine-grained approach to MTCMOS.

"The challenge with power gating is when to use the coarse- or fine-grained approaches," Chai said. TSMC believes that "if the customer uses a combination of techniques, they can get a good handle on power."

"In the middle of last year, people started talking about all kinds of things to keep power under control," said Anand Iyer, a strategic-marketing manager at Cadence Design Systems Inc. "Then, toward the end of the year, we found a trend: Power shutdown emerged as a major technique. It became very apparent that to be in the 2.5G cell phone, it was OK to do well biasing and these kinds of things. But to be in the 3G [third-generation] box, with its more stringent limits on power consumption, designers have to employ power shutdown."

Every step of the design methodology is affected by the inclusion of power-gating transistors, Iyer said.

RTL synthesis must be able to insert the token switch cells; these may not represent the complete switch cell, but indicate that a certain region can be shut down. If a design requires state retention, RTL synthesis must include that. And during physical implementation, the switch configuration and placement all become an issue.

"I have seen some designs where they have strewn power gate cells around, not a structured approach," Iyer said. "I have seen both, structured and not. The coarse-grained approach is being adopted by leading and mainstream companies, but it requires work on the physical implementation and placement to optimize the switch. It requires creativity and imagination on the part of the designers."

In a sense, shutting down a circuit is just one form of a multi-V_dd approach, said Jason Cong, a UCLA professor who is doing research into behavioral synthesis and statistical optimization. "Power gating is almost the extreme of the multi-V_dd, except that one of the V_dd's is zero," he said.

Turning circuits on and off is a complex undertaking, spawning whole new fields of research and a new class of design tools. Just as the DSP and computer processor vendors have moved to multicore designs to cope with power, designers may be forced to move to new design methodologies.

Cong argues that the challenges of power gating may lead more chip designers to use behavioral, rather than register-transfer-level, descriptions. Though Synopsys Inc. and others tried to find acceptance for early behavioral-synthesis tools, RTL has remained king of the hill.

"Behavioral synthesis could be more successful this time because of power," Cong said. "Designers need to start to write circuit descriptions at the behavioral level instead of at the RTL level. They need to think about the functionality of the circuit. They have to know what parts of the device can be shut down. They have to think about temporal and spatial information."

For example, he said, "if a set of components can be shut down, they may want to put them together. That may affect the delay, the scheduling, in the microarchitecture. All of that is interleaved, which presents a challenge to the RTL designer today. So it would be very attractive for behavioral synthesis to automate that process."

Andrew T. Yang, co-founder of Apache Design Solutions Inc., said most designers must choose between a coarse-grained approach, in which whole blocks are turned off, and a fine-grained approach that may add tens of thousands of power switches, which can bloat the die size. Apache offers a synthesis tool, called LP RedHawk, that models the chip's performance and power leakage in order to place and route the correctly sized power switch transistors. The tool has been incorporated in the reference design flow supported by TSMC.

"Just about all semiconductor companies are putting power switches into their designs," Yang said. "But our position is that clock and power gating must be dynamic, so they can be turned off and on in real-time."

Chip makers' perspective
Rick Hetherington, a distinguished engineer at Sun Microsystems Inc. who was chief architect of the Niagara multithreaded processor, said the Niagara designers concentrated on two areas that reduced peak power: controlling the instruction issue rates of the Sparc cores and limiting activity in main memory.

Niagara has a mechanism to throttle issue rates within the cores by putting specified threads in a sleep mode, Hetherington said. When power and thermal conditions return to normal, threads resume issuing and executing instructions.

At the end of the Niagara pipeline is the second source of high power consumption: the DDR2 memory controller. On a server, approximately one-third of total system power comes from memory. Niagara has four DDR2 memory channels, each supporting four DIMM slots. Under peak periods, software-enabled control registers limit the number of open pages in the DDR memories. "Spreading a reduced number of DRAM activations over a longer time period is one good way to reduce DRAM power consumption," Hetherington said.

For its part, Texas Instruments has developed peripherals that can be autonomous, Buccini said, with control that is independent so the CPU does not have to be awakened. "The peripheral detects a valid match to an address, and then wakes up the CPU," he said. "It is part of the overall goal of keeping everything as calm as possible so that circuits are only active when required, and then everything shuts back down."

By paying attention to code size, off-chip accesses and power gating, designers are making progress in keeping within their power budgets. But "getting in and out of sleep and standby modes is not a trivial thing," said John Dixon, a DSP product manager at TI.

At present, several members of the company's TMS320 C5000 series DSPs support dynamic frequency and voltage scaling. A DSP power manager is included in the BIOS. With TI's Code Composer Studio tool suite, engineers can set the frequency and voltage dynamically within their code, choosing from among 16 set points.

A research group at TI's Santa Barbara, Calif., R&D center is working on an intelligent operating system that looks at the code and automatically adjusts the frequency and voltage.

For now, however, "there is no magic button that we can press," Dixon said. "It's a series of techniques, each of which can reduce power by some percentage, which at the end can be a huge factor. And we try to help customers not fall into traps which add power back into the system."

Analog Devices Inc.'s Blackfin DSP architecture, meanwhile, supports five power-down modes, ranging from full-on to deep sleep, said Wayne Meyer, an Analog Devices product manager. "We have a software-programmable PLL which lets the user throttle the megahertz back, using only as much voltage as necessary," he said. While the Blackfin can operate at 600 MHz at 1.2 volts, it can run on as little as 0.8 V, delivering 200 MHz at "huge power savings," Meyer said.

ARM Ltd. is working on a whole raft of tools within its Intelligent Energy Manager (IEM) tool suite, said Kevin McIntyre, power-management product manager at the embedded-processor vendor. The IEM suite works with the operating system to initiate the most aggressive power-saving techniques possible.

"The first OEM products using some of these techniques will come to market in the next four or five months, and we believe they will offer system [power] savings of 25 to 50 percent," McIntyre said. "The goal posts keep moving. With the 3G cell phones, talk time is a big challenge and battery life is not very good at all. With MP3 playback and video coming, it is only going to get worse."

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