Meeting timing at the worst or best-case corner can be very challenging, lengthening design schedules and negatively impacting power consumption. With a large range of potential delay values, often with a difference of as much as 50 percent or more between the slow and fast process corners, it becomes harder to meet both setup times at the worst-case corner and hold times at the best-case corner.

Even if the performance goals are met, there is often an undesired impact on other design metrics, in particular power consumption, noise immunity and leakage. For example, to meet an aggressive performance target, optimization may deploy a higher ratio of low threshold cells that are faster but leakier. With statistical analysis, a better tradeoff between timing and other design metrics such as power, noise immunity can be achieved.

SSTA provides not only a list of worst timing paths, but also the probability of those paths failing while accounting for the impact of process variation. To accurately predict variation, it needs to account for both systematic variations (one example would be due to lithography) and random variations (one example would be due to doping).

Even within the same chip there is a wide range of on-chip variation (OCV). Traditional static timing tools use guard-bands or OCV factors (often as much as +/- 15%) to safeguard against OCV, but this type of over-design is too wasteful to be effective at 65nm or below. This is because at the smaller geometries the process is more sensitive to variation and over-design has an even bigger impact on leakage power. Furthermore, many of the advantages of using a costlier process node may be eliminated if too many cells are needlessly over-sized to meet an unrealistic OCV target.

SSTA can help provide a much more realistic measurement of OCV that reduces the overall guard-band but also protects against corner cases where a single large OCV factor is not sufficient to catch potential errors. This is because each transistor in the design will have a unique sensitivity to each source of process variation depending on its size, location, orientation, interconnect loading and how it is driven.

Shown in figure 1 are the delay cumulative distribution functions (CDFs) for an inverter when subjected to three different input slews and three distinct output loads, nine cases total. The curves were calculated by Monte Carlo simulations varying the transistor width (XW), length (XL), threshold voltage (Vth) and oxide thickness (TOX).

From the slope of these curves, it is clear that the delay sensitivity to variation changes with the environment that a given instance of a cell is associated with. In addition, OCV de-rating is often applied without consideration of the path length where for longer paths the probability of accumulation of random variation is much smaller than for short paths. Consequently, a single one-size-fits-all OCV factor approach is both costly and not very effective.

Figure 1 — Cumulative distribution functions of delay vs. skew and load

While variation can impact both cells and interconnects, it has a larger overall impact on cell performance. Critical to effective SSTA are the statistical cell models that SSTA is based on. These models can be created by pre-characterizing each cell under different loading and slew conditions while accounting for a range of process parameter variations based on actual process data and measurements.

Statistical timing models

SSTA requires a cell model that accounts for process parameter variations. Typically the important process parameters for SSTA are transistor channel length (L) and threshold voltage (Vth), though in general any process parameter may be modeled for variation. Each process parameter may vary either globally, systematically or randomly. Global variation, systematic variation and random variation have monotonically decreasing characteristic distance, or effective range of the variation impact.

Global variation is usually associated with different process steps in the chip manufacturing process. Each of the global variation parameters, such as L, W, Vth and gate oxide (TOX), impacts a wide region, perhaps over an entire chip or even across multiple chips on a wafer, but its impact is rather uniform across the region.

However, different global parameters may not be correlated in their variation. For example, lower dopant concentration (which affects Vth) and thicker gate oxide (TOX) than nominal may occur simultaneously across a wafer, but their impact on timing is the opposite. Each delay, transition, setup/hold, and pin capacitance table entry needs to be characterized for each global variation parameter.

The total timing sensitivity depends on the correlation between the global parameters, as well as between NMOS and PMOS transistors which may vary independently. For every library data value, multiple simulations are required to characterize global timing sensitivity, and non-linearity in the variation impact on timing must be considered as well.