Santa Cruz, Calif. -- FPGA complexity and speed are rapidly increasing, and as a result, FPGA designers are confronting many of the same issues--and adopting some of the same tools--as their counterparts in ASIC and IC design. That's the picture that emerged from the FPGA portion of the "EE Times 2006 EDA Users Survey," which was released at last week's Design Automation Conference.

The FPGA survey was completed by 230 engineers, including 116 from North America, 42 from Europe and 65 from Asia. About 80 percent are design engineers, with the remainder in engineering or corporate management. Companies of all sizes are represented.

These engineers are expecting average gate counts of around 4 million within two years. While meeting timing budgets is the prime concern today, our North American FPGA respondents, just like the respondents to the ASIC portion of the survey, said that leakage current is getting notably worse as silicon geometries shrink.

There are other ways in which the FPGA survey results mirrored those in the ASIC survey. In both cases, EDA budgets are rising faster in Asia. In both surveys, designers are most satisfied with the accuracy of their EDA tools, and least satisfied with pricing and interoperability. And in both surveys, North American designers were generally more satisfied with tools and vendors than respondents to EE Times' 2005 survey, which focused on North America only.

The 2006 survey also shows that tools and technologies from the ASIC world are seeing broader acceptance. Huge majorities are using FPGA synthesis, HDL simulation and FPGA floor planning, and there's growing interest in hardware/software co-design, power analysis, SystemVerilog and C-language synthesis.

What they're designing
Most respondents from all three geographies are using FPGAs for production rather than prototyping. The use of FPGAs for prototyping is highest in Asia (42 percent) and lowest in North America (18 percent). The average number of FPGAs in current designs is between two and three, and the expected average in two years is over three, in all geographies.

Asked to specify the total equivalent gate count of the largest FPGA currently in progress, North American engineers came up with a mean count of 2.4 million, European engineers with 3.1 million and Asian engineers with 2.3 million. Two years from now, the respondents expect mean gate counts of 3.9 million, 4.3 million and 3.6 million, respectively.

Clock speeds are on the move, too. The mean clock speed cited by North American engineers for current projects is 188.5 MHz, with 327.8 MHz expected in two years. Results for Europe and Asia are slightly higher.

The proportion of logic gates taken up by reused intellectual-property (IP) blocks is 37.1 percent in North America, 28.9 percent in Europe and 35.2 percent in Asia. However, the survey found that just 40 percent of North American designers are including DSP blocks in their FPGAs, down from 56 percent last year. And 36 percent are using microprocessor cores, down slightly from 40 percent.

Timing now, power later
The primary technical challenges identified by North American FPGA designers at current process geometries are meeting timing budgets, getting the FPGA to work on the pc board and completing functional verification. These three issues are high on the list for European and Asian respondents, too. But when asked what's getting worse as process geometries shrink, North Americans pointed most to managing complexity and meeting leakage power budgets. Europeans and Asians focused on complexity and seemed less concerned about leakage.

EDA tool budgets are rising, but they're rising fastest in Asia. Among the survey respondents, 50 percent of North Americans, 58 percent of Europeans and 80 percent of Asians said their 2006 budgets are "more" or "much more" than they were in 2005. Last year, only 39 percent of North Americans said their budgets had increased over 2004.

The cost of the most recent FPGA design project ranged from a mean of $285,300 in North America, dropping to $204,200 in Europe and just $45,900 in Asia. It should be noted, however, that the sample sizes for this question were relatively small.

ASIC tools, methodologies
The days of designing FPGAs with schematics are gone. Our survey showed that 94 percent of North Americans, 95 percent of Europeans and 91 percent of Asians are using FPGA synthesis. Solid majorities in all areas are using FPGA place and route, FPGA floor planning and HDL simulation.

What may be most interesting is the growing appeal of methodologies that are still emerging in the ASIC world. For example, 33 percent of North Americans use hardware/software co-design today, and an additional 32 percent expect to use it in two years. SystemVerilog is used by 20 percent today, and an additional 41 percent expect to use it in two years.

Evaluating the vendors
Asked about overall impressions of EDA vendors, respondents in all three geographies were most positive about technology, ease of use and support. Pricing, licensing and interoperability ranked low. Compared with last year, North Americans are significantly happier about the quality of software.

Xilinx is the most broadly used EDA vendor, with 93 percent of North Americans, 88 percent of Europeans and 91 percent of Asians using the company's tools. Following Xilinx, in order of use, were Altera, Synplicity, Mentor Graphics, Cadence Design Systems, Mathworks, Synopsys, Actel, Lattice and Aldec. North Americans have significantly expanded their use of Xilinx and Cadence.

Compared with 2005, North Americans are more satisfied with Synplicity, Xilinx, Mentor, Cadence and Lattice, and especially Aldec, which went from 44 percent to 67 percent. But satisfaction slipped for Altera, Synopsys and Actel.

Xilinx topped the rankings for a number of criteria, including best after-sales support, best documentation, competitive prices, technology leader today, technology leader in three years, best support of open standards, knowledgeable sales reps and best integration with other vendors' tools.

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