While the proposals are still in an early stage and could be applied to a variety of uses, they clearly target the heart of the Torrenza program at Advanced Micro Devices Inc.

Code-named Geneseo, apparently for a small town in New York, the proposals aim to extend PCI Express in four broad areas. They include providing more fine-grained power management, a locking mechanism for shared memory, hints to help a coherent processor more effectively handle I/O and memory and protocol efficiencies for mapping virtual to physical memory.

The resulting improvements fall significantly short of creating a cache coherent version of PCI Express. As such they do not fully provide all the technical underpinnings of cache coherent HyperTransport (cHT) that is at the heart of AMD's Torrenza program. Nevertheless, functionally the Express extensions aim to address many of the same core uses as Torrenza including providing a standard connection between a processor and accelerators cores for functions such as graphics and XML processing.

In that sense, a big part of the motivation for Geneseo is stealing the wind from AMD's sails as it tries to capture interest from third party chip makers and OEMs. "At the highest level, that's exactly what's going on," said one source familiar with both proposals.

"I don't see anyone thinking about doing a coherent version of Express. It's not the right approach. So to some extent this is technically apples and oranges and for certain workloads the AMD approach will be a better fit," the source added.

Marty Seyer, senior vice president of AMD's commercial division, took a conciliatory view of the news. "We see multiple levels of co-processing ranging from this latest proposed PCIe approach, to the ultimate of direct connect into HyperTransport. AMD supports them all as long as they drive open innovation."

Other Geneseo backers include Broadcom, Cisco, Dell, EMC, Hewlett-Packard, LSI Logic and Sun Microsystems. It's unclear how far the group is in its work, but one release did characterize Geneseo as a set of discussions rather than a finished specification.

The Geneseo group has put forward some of its ideas as proposals to the PCI Special Interest Group where they are under study. The more straightforward proposals such as providing more power management levels on Express could be turned into a spec in as little as six months.

More complex proposals such as defining locking mechanisms and coherency hints would require a careful evaluation of the different coherency protocols used by AMD, Intel, IBM and Sun. That job could take a year to reach a spec.

AMD has been in discussions with a host of computer industry companies about licensing cHT, which it uses natively on all its Opteron processors. The company has also been seeking broad input on the specs for its next-generation Opteron socket that will accommodate at least three cHT links.

Geneseo is supported by several companies including Adaptec, AGEIA, Altera, Broadcom, Celoxica, Cisco Systems, ClearSpeed Technology, Dell, EMC, Emulex, HP, Integrated Device Technology, Lecroy, Linux Networx, LSI Logic, Mellanox Technologies, Myricom, NetEffect, Novell, Nvidia, PLX Technology, PMC-Sierra, QLogic, Sun Microsystems, Synopsys, Tektronix, Xambala Inc., Xilinx Inc. and Xtreme Data.

PCI Express technology was first delivered in client and server computing platforms in 2004. Its introduction signaled the transition of computing platform I/O from the parallel bus model that had existed since the PC industry's inception to a high-speed, serial I/O standard.