Unlike other solutions that require different controller types for different types of memory, emBISTRx uses a hierarchically distributed architecture with a centralized BIST/BISR controller. This approach claims to reduce area by 20 to 30 percent compared to existing BIST solutions.

The emBISTRx offering also claims to reduce the number of interconnects and routing congestion, resulting in area savings and faster timing closure. It provides an automation tool to insert and stitch the BIST and BISR logic into the design. And it includes algorithms that detect such defects as excessive leakage, weak bits, and resistive shorts and opens.

ARM developed its own technology because it has a "deep understanding of the physical aspect of embedded memory," according to Ramamurti Chandramouli, senior product marketing manager for ARM's physical IP division. "Generic EDA tools do not have access to memory IP [intellectual property] topology and physical architecture," he said. "They lack the knowledge of process defect histories and are not cognizant of a particular memory design approach." Some third-party tools, he noted, cannot support both row and column repair.

The emBISTRx solution, Chandramouli said, simplifies design complexity by distributing test and repair intelligence across multiple hierarchy levels of the embedded memory subsystem. ARM's integrated test and repair architecture allows faster timing closure and minimizes design iterations, he said.

"Finally, creeping elegance in algorithms chasing unrealistic faults has added to the complexity and the area of competing integrated test and repair solutions," Chandramouli said. "On the contrary, the ARM emBISTRx solution has simplified the test and repair algorithm focusing on real-world defects to achieve better quality and reparability."