Semiconductor process technology has been continually scaling down for the past four decades, and the trend will continue for the next one or two decades. In the early days of integrated circuits (ICs), the speed bottleneck was at the transistor level, whereas interconnects were treated as ideal connections with the parasitic effects ignored. With shrinking process technologies, as well as increasing die size and clock frequency, interconnect parasitic effects have begun to manifest themselves in signal delay and noise. Consequently, interconnects now play an important role in the design flow. Today, IC design is interconnect-limited, and the design flow is interconnect-driven.

Previously, it was adequate to model interconnects with parasitic resistance and capacitance (RC). There have been many well studied methodologies for simulation, design, and optimization of global interconnects based on RC models. As clock frequencies increase, however, modeling global interconnects such as RC circuits is no longer adequate, and inductance must be included in the modeling. Fast and accurate inductance extraction is the first step in studying high- frequency effects. The inductance matrix for interconnects is dense and slows the circuit simulation. Thus, a fast and accurate resistance, inductance and capacitance (RLC) simulation methodology is critical to the analysis and design of high-speed interconnects. In this article we describe a novel and practical approach to modeling inductance effects.

When Should We Consider Inductance in a Design?

There is no simple answer to this question. The most straightforward guideline is that jωL, the imaginary part of impedance, should be comparable with R, the real part of impedance. However, it is just one of the necessary conditions. The transition time should be smaller than the round-trip delay. Additionally, the driver resistance, line resistance and load capacitance should be small as well.

The inductance effect becomes more and more prominent as the resistance (both device and interconnect) decreases and the operating frequency increases. At low frequencies, RC modeling is sufficient, and inductance can safely be ignored. At high frequencies, inductance should be incorporated using a RLC model. Ignoring the inductance effect can underestimate signal integrity problems as well.

Partial Inductance Approaches

Traditionally, inductance has been a concept for closed conductor loops. For on-chip interconnects, the signals and their return paths form the loops. Typically, each signal has many possible return paths. The return current always tries to find the return paths with minimum impedance. The "effective" loop inductance, which is determined by the signal itself and the current distributions in the return paths, can be used in delay or signal integrity analysis. However, because of the complex power grid and signal line structures, it is very difficult to determine the current return paths for on-chip interconnects in real designs. The current distribution is needed to define the loop inductance, and typically current distribution is unknown prior to extraction and simulation. Thus, on-chip inductance and the circuit return path become a "chicken-egg'' paradox.
To overcome this difficulty, Rosa developed the concept of partial inductance, and Ruehli introduced the Partial Element Equivalent Circuits (PEEC) model for general on-chip interconnect analysis (References 1 and 2). These methods allow the loop inductance to be represented by a series of independent partial inductances that can be analyzed without knowledge of the full return path. Partial inductances can be recombined during simulation to reconstruct the original loop inductance. Thus, the PEEC model and the partial inductance concept are now widely used in interconnect analysis as they do not require the definition of current loops a priori.

Since partial inductance is based on the virtual loop closed at infinity, the couplings are now among all the conductor segments, and the resulting partial inductance effect is global. Due to this global effect, the partial inductance matrix is extremely dense, while the capacitance effect is local and its matrix is sparse. Figure 1 compares the locality of capacitance and partial inductance.

Because it is very expensive to handle large, dense matrices in parasitic extraction and circuit simulation, the partial inductance approach is impractical for capturing inductance effects of on-chip interconnect from large designs, and techniques for sparsifying the inductance matrix are necessary. The direct way to sparsify the partial inductance matrix is to truncate the small terms in the matrix that has been widely used for capacitance extraction. But, unlike the positive definite characteristics of capacitance matrix, the truncated partial inductance matrix may no longer be positive definite, and the simulation may fail to converge. Even though several sparsification methods have been proposed, the accuracy or efficiency of such approaches are not guaranteed under different interconnect topologies as they assume artificial current return loops. These ad-hoc methods produce inductance netlists; however, they are inaccurate.

Reluctance Extraction " An Elegant Approach to Inductance Matrix Density

A practical method for inductance extraction must not make ad-hoc assumptions. It must, however, produce netlists small enough for fast simulation. Devgan, Ji and Dai introduced the partial reluctance circuit model in 2000 (References 3 and 4). They pointed out that partial reluctance has locality similar to capacitance, and it can be sparsified like the capacitance matrix without losing the passivity of the circuit. Reluctance is defined as inverse of inductance, [K] = [L]^-1. From the definition of the partial inductance matrix [L], the partial reluctance matrix [K] can also be defined as the ratio between current and the integration of vector potential drop along the conductor segments. By inverting the partial inductance matrix to the partial reluctance matrix, it can be found that the partial reluctance matrix has similar sparsity to capacitance matrix, and it is much sparser than the partial inductance matrix. The following Figure 1 shows such properties for a 7-bit bus-line structure.

Reluctance coupling is local because reluctance is shielded by neighboring conductors, while inductance has no such effect and is mainly a function of distance between wires. The following Figure 2 compares the locality of the normalized partial reluctance and partial inductance for a 15-bit bus-line structure.