SiPs pack multiple die into an IC package, and may even stack up multiple packages in package-on-package (PoP) or package-in-package (PiP) arrangements. SiPs may include logic and memory ICs, as well as analog circuitry and embedded passive components. They're attractive for consumer applications such as cell phones because they can potentially speed development times over highly integrated SoCs.

But SiPs require a new approach to design, said Matthew Kaufmann, director of IC assembly and package development at Broadcom Corp. Today, he noted, IC design, package design, and pc-board design are all discrete disciplines — and that has to change.

"SiP represents the convergence of IC, package, and PCB design, and all these things need to be integrated together," Kaufmann said. "You will now have to take on things that are beyond the traditional scope you've worked on. Tool capabilities will have to integrate all these concepts."

Packaging is the "poor stepchild" of the electronics industry, Kaufmann said, with no consistent tool set that allows integrated design and analysis. Current tools come from a "PCB mentality" and primarily focus on layout, he said. Handoffs between design domains are "quasi-static," and hard-coded rules don't work for SiP interconnect. In addition to layout, Kaufman said, there's a need for analysis of thermal, electrical, manufacturability, process, and quality characteristics.

Infineon is working with complex, high-pin count SiPs that require IC/package/PCB co-design, said Jochen Reisinger, director of Infineon's co-design project. "It is very important that the early design work be done with the same flow and tools," he said. "It doesn't make sense to do some paperwork, throw it away, and then go into system, package or IC execution."

Current gaps in the SiP tool flow, Reisinger said, include multi-level constraint management, multi-technology tool support, 3D standard exchange formats, multi-level simulation support, multi-level models, mixed-level verification, and connectivity support. While board designers use IBIS models, he noted, they don't allow one to execute a system simulation with transistor effects.

A standard data format between IC, package and pc-board design tools would greatly help, Reisinger said. "We are putting huge efforts into driving standards to get common data interchange formats," he said. Also needed, he said, is consistent constraint management across all three domains.