A typical design project goes through 10 or more iterations due to timing constraint refinement. Poor constraints impact the chip quality in terms of area, power, and timing. Subsequently, timing closure takes longer. Worst of all, incorrect constraints could result in silicon failing timing and resulting in a re-spin. There is a critical need for an EDA solution to ensure that correct timing constraints are generated and used in the design flow. Atrenta's SpyGlass-Constraints is an example of a tool that has successfully provided a validation solution to ensure the correctness, completeness and consistency of the timing constraints through a design flow (Figure 1).

1. Constraints validation focused flow requires intervention at multiple points in design flow.

In a typical design flow, the designer creates a functional description of the design in RTL, along with the timing constraints Throughout the design flow, be it synthesis, floor-planning or place and route, the user manually updates the constraint file at each step either to add missing constraints and/or exceptions or to correct them to meet area, timing and power requirements. Where as constraints validation helps reduce the pain by validating constraints at each step in the design flow, what designers need is a mechanism to generate correct by construction constraints to eliminate the source of the pain in the first place.

2. Constraints generation focused flow simplifies the design flow by using correct by user techniques.

Designers need an automatic creation of a "correct" and "complete" set of timing constraints to begin a design flow. This limits the need for checking constraints at different stages of the design to only those that are added by the user (Figure 2).

The timing constraints (SDC) creation must have three important aspects:

• "Complete" set of constraints includes clocks, input and output delays, clock latency, clock uncertainty, set-case-analysis, clock and input transition, output load, max and min delay, false path exceptions and multi-cycle exceptions paths. False path exceptions include clock domain crossing, asynchronous reset, scan enable and the false paths created using functional analysis of the design. Missing constraints can significantly affect the quality of results.
• "Correct" set of constraints means there is no need to validate the constraints through external validation tools. This also includes timing exceptions, which should be functionally correct by construction. Incorrect timing exceptions may lead to silicon timing failure as they can mask silicon timing issues through the implementation steps.
• "Meaningful" constraints refers to the appropriate set that will not overwhelm but instead help the downstream tools, like synthesis and physical design, to produce better chip QoR in terms of area, timing and power.