In the case of digital integrated circuits (ICs including ASICs, ASSP, and systems-on-chip), many people seem to have the impression that the transition to the 65 nm technology node is proving to be "not as bad as expected." In reality, however, we are in the eye of the storm. So far, only a small number of chips have taped out with apparent success. However, there's a gap between tape-out and production. Reports are now coming back that yields are lower than even the pessimistic expected.

Why are Manufacturability and Yield Important?
In the context of digital ICs, the phrase design-for-manufacturing (DFM) refers to a variety of techniques used during the process of implementing the design to ensure that it can be manufactured correctly. Meanwhile, the term yield refers to the number of die that work as a percentage of the total number of die on the silicon wafer. Hence the phrase design for yield (DFY) refers to any techniques used to improve the yield of a particular device. In reality, these techniques are so intertwined that it is becoming common to consider them as being a single entity: DFM/DFY.

Yield is a function of the device's manufacturability and there are three main "buckets" into which yield-related problems may be categorized. These buckets are commonly referred to as Random Yield (sometimes called Statistical Yield), Systematic Yield, and Parametric Yield.

1. These are examples of yield loss due to random, statistical and parametric effects.

Random (Statistical) Yield
As its name suggests, this form of yield is a function of random effects that occur during the manufacturing process. For example, no matter how clean the wafer manufacturing environment, there are always some number of small particles in the atmosphere that may land on the surface of the chip.

Such particles may cause catastrophic faults in the form of open or short circuits. Alternatively, in some cases they may cause parametric variations. For example, a particle may land on a non-critical area of a particular layer and may cause a non-planar feature (bump) in subsequent layers. In turn, this bump may end up varying the width or thickness of a wire on a higher layer, changing the electrical characteristics of that wire and resulting in a parametric yield failure (as discussed below.)

By their very nature, random defects are difficult to control. However, it is possible to create the design in such a way as to minimize their effects on final yield.

Systematic Yield (Including Printability Issues)
The term "systematic" encompasses the concepts of "logical," "methodical," and "ordered." Thus systematic yield refers to a class of manufacturability issues that are the result of some combination and interactions of events. These issues can be identified and addressed in a systematic way.

Many systematic yield issues are design-dependent. For example, some designs may have high densities (concentrations) of wires in certain areas and low densities in others. Such density variations can affect the amount of etching that takes place in the various regions. Similarly, in the case of process steps like chemical mechanical polishing (CMP), variations in wire density can cause differences in the effectiveness of the polishing process, which can result in areas where some wires are thinner than others. In turn, this affects the resistance and capacitance values associated with these wires, which can modify the power and performance (timing) of the design.

By understanding systematic effects during the design implementation process it is also possible to create a design in such a way as to minimize their effects on yield.

Parametric Yield (Including Variability Issues)
The concept of parametric yield refers to the fact that a chip may perform its logical function correctly ("stimulus X returns response Y"), but variations in the device's parameters may mean that it does not achieve its specified performance goals. If transistor channels aren't formed quite as expected, for example, the result may be lower drive capabilities, increased leakage current and greater power consumption, increased resistance and capacitance (RC) time constants, and slower chips.

Alternatively, issues in the etching and CMP processes may cause non-planarity in the surface of the chip, which, in turn, can cause wires to have higher resistances and/or capacitances than expected, which will result in the device's speed falling and its power consumption rising.

One aspect of parametric yield that is becoming extremely significant is that of variation or variability. There has always been an issue with regard to inter-wafer variation, which refers to slight differences between wafers in a lot. In the case of today's technology nodes, there can be significant variations between different areas on the same wafer (intra-wafer variation) and even the same die (OCV or on-chip-variance).

By understanding parametric effects during the design implementation process it is possible to create designs that minimize loss in chip performance and yield.

So Why Are Yield and Manufacturability Important?
The reasons yield and manufacturability are important may be summarized as follows:

• The chips (and associated products) may completely miss the market window.
• The chips (and associated products) may hit the market window, but the chips may cost too much to make the products economically viable.
• The chips may not perform at required level; that is, they still may function, but not at the required speed.
• The chips appear to be reliable after volume production, but may suffer catastrophic failures in the field earlier than their expected lifecycle.

The bottom line is that if DFM/DFY issues are not addressed, it may simply not be possible to achieve economically viable yields in the forthcoming technology nodes.