To create a comprehensive verification solution, we must first acknowledge both the differences and the challenges that designers and verification engineers face. In the process, we find that certain gaps are inadvertently neglected. The first major gap that is commonly overlooked is "reuse." Often, block-level verification environments are not leveraged within the cluster level (subsystem) or the chip level, which presents a major problem.

Traditionally, we see block-level environment development created by design engineers who have been verifying connectivity and simple interfaces. These designers, although skilled, often pay only precious little attention to those very aspects of verification that will allow for reuse, such as coverage. Coverage, as we know, is becoming a more and more critical priority and can include functionality, code, assertions, low power, toggle, and even software.

What is needed are solutions that allow design and verification engineers to capture the system-level (hardware and software) specifications and coordinate them with the design intent as early as possible in the design and verification cycle. These solutions will require the early development of software and analysis of hardware, as well as the creation of a robust early system-level verification plan. The bottom line is that the verification process needs to be broken down into three major flows.

First, extended teams will need to verify the critical phases of any complex chip design. Overall architecture will need to be analyzed, and models using high-level abstraction languages such as SystemC or C++ will have to be taken into consideration. In this early phase, portions of the design modules must be modeled within high-level, system-level interfaces and validated early within the software development period.

There are two benefits here: the early ability to debug architecture holes in the hardware and software, and potential performance advantages of using transaction-level models (TLM). It is important to ensure that the architecture-level flows are developed and maintained by verification engineers working closely with architecture and software teams.

The verification phase is precisely where a SoC verification kit adds a tremendous amount of value. A well-assembled verification kit allows users to easily access many of the powerful aspects of verification, such as formal analysis and assertions and coverage, driving toward system-level closure. In this flow, designers and verification engineers are able to reuse some of the transaction-level models from the architecture flow and also scale the environment upward to complete the sock-verification environment.

As chips for the latest consumer products become smaller—and designers need to pack growing numbers of design elements in less space using advanced power-reduction techniques—verification of these techniques becomes more critical than ever before. Engineers must consider the various power-saving modes, ensure proper functionality, and make sure the overall coverage is accounted for. Users must consider dynamic testing, dynamic and static assertions, and basic functional-verification methodology that takes them from an initial plan to verification closure.

This phase includes advanced in-circuit emulation and transaction-based hardware acceleration (TBA). By considering solutions such as emulation and acceleration, users will find that the verification environment again has the ability to be reused at the system level, allowing actual software to be run, thus enabling both hardware and software debugging and co-verification at speeds much greater than in TLM or RTL environments.

During microarchitectural implementations, it is critical to analyze complexity and performance. Design engineers must work closely with dedicated verification engineers to ensure proper reuse of verification components, legacy tests, and coverage and compliance checks. Scalability needs to start from block level and move to system level as designers keep both hardware and software in mind. Furthermore, testbench development and planning must last from early architecture modeling (Flow 1) through post-silicon validation (chip bring-up) while keeping in mind the ultimate benefits of a "kit" that is ready to jump-start the entire process.

—Amjad Qureshi is director and digital kits architect at Cadence Design Systems.