BENGALURU, India -- As semiconductor geometries continue to shrink, the people who have to deal with that trend face confounding challenges of manufacturability, complexity and scale.
For Cadence Design Systems Inc., a major EDA player, and Michael J. Fister, its president and CEO, that means looking at the design process from a different angle.
Fister, speaking at the annual user meeting CDN Live India 2007, said maintaining manufacturability of advanced process nodes at 90 nm and below as well as the complexity of systems-on-chips presents diverse obstacles, including chemical mechanical polishing, or CMP, and lithography. In fact, he said, all the issues are quite complicated, made more so as foundries bite off bigger shares of the global IC market.
Manufacturability problems may be tackled, he said, by adopting an electrically aware design-for-manufacturability mindset, marked by a thought process that combines prevention, analysis and optimization, in addition to model-based verification.
"Augmenting manufacturability of devices needs proactive integration of manufacturing elements into design, a dramatic evolution of the process of the last 15 years. It is totally necessary to enable continued migration down Moore's Law. The core of automation is to test all the kinds of conditions," Fister said.
On the complexity and scale of designs, the challenges include design size and the need to inculcate multiple protocols. Here the solution is to have a holistic design involving end-to-end power management, uniform timing engine and advanced functional verification. Fister said.
Cadence is adopting such a holistic method, and through its kits it is looking at optimizing and not merely integrating the various design elements. "The kits' approach is a big idea, but a long-term one and parallels the solutions approach other industries have taken. The kits are innovations from the top--and not reinventing the wheel--and the smaller companies have especially found the kits useful," he said, adding that the motive at Cadence is to integrate more semiconductor experience into the company.
Fister said he sees the fabless approach gaining pace and, in turn, causing the need for a more solid design methodology. As design types and techniques spawn an almost infinite number of design methods, the kits help to inculcate a methodology and eliminate some of the permutations, he said. "We are enabling the fabless evolution to be more predictable, in its utility and yield in its broad sense " timing, performance and the like," he said.
Interestingly, for the first time perhaps in its history, the industry is engaging in more process generations simultaneously, not just in design but also in manufacturing, he said. "This allows a very important mindset as you can take techniques that would have only been applied in forward-looking geometries and apply them in a kind of a backward extension--such customers present us with a lot of value. They are taking some techniques of 45-nm and 65-nm and applying them in 90-nm or even 130-nm. So they may even get the net effect of operating on a technology and scaling to a future technology without even having moved."
He said it would be a mistake for the industry to merely focus on whether designs are happening for 45- or 65-nm process technology. The reason: that would risk missing the chance to catch the momentum of design or also miss the conservationism of what methods apply at whatever process node the customer is operating in.