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Cadence, Mentor roll verification tool
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EE Times


Cadence Design Systems Inc. and Mentor Graphics Corp. said Wednesday (Jan. 9) they have released Open Verification Methodology (OVM) software for chip verification.

OVM souce code, documentation and user examples will be distributed under a standard open-source licenses, the companies said.

The interoperable SystemVerilog methodology can be downloaded from the OVM Web site.

Cadence (San Jose, Calif.) and Mentor (Wilsonville, Ore.) said in a statement that OVM includes foundation-level utilities for building object-oriented, coverage-driven verification environments and reusable verification IP in SystemVerilog.






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